Class 327/210 - CMOS

Subclass of Class 327 - Miscellaneous active electrical nonlinear devices, circuits, and systems
Definition: Subject matter wherein the FET is of the complementary
No. of patents: 195
Last issue date: 12/06/2011

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Number	Title	Issue Date
8072252	Compound logic flip-flop having a plurality of input stages A compound logic flip-flop. The flip-flop includes a plurality of input stages, wherein each of the input stages is coupled to receive at least one input signal and a clock signal. Each of the plurality of input (i.e. ‘master’) stages is configured to perform a ...	12/06/2011
7724057	Current-controlled CMOS logic family Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, X...	05/25/2010
7557630	Sense amplifier-based flip-flop for reducing output delay time and method thereof A sense amplifier based flip flop and method thereof are provided. The example sense amplifier-based flip-flop may include a first current passing unit receiving a first clock signal with a first delay, the first current passing unit configured to pass current from ...	07/07/2009
7486124	Current-controlled CMOS logic family Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, X...	02/03/2009
7446581	Semiconductor integrated circuit with a logic circuit including a data holding circuit A semiconductor integrated circuit includes a first data holding section, a first pull-up circuit, a first pull-down circuit, a first feedback circuit, and a second feedback circuit. The first data holding section holds first output data. The first pull-up circuit t...	11/04/2008
7437800	Clock gating circuit Clock gating circuits are disclosed in the present disclosure. Also disclosed herein are methods for designing clock gating circuits in the early stages of manufacturing. In one embodiment of a method for designing a clock gating circuit, the method comprises provid...	10/21/2008
7405606	D flip-flop A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback ele...	07/29/2008
7368955	Current-balanced logic circuit In accordance with some embodiments, a current-balanced logic circuit includes a first sense amplifier, a second sense amplifier, and a current-source transistor which provides bias current to the first and second sense amplifiers. The first and second sense amplifi...	05/06/2008
7366623	Method and apparatus for characterizing a load on a data line A method for characterizing a load on a data line includes the steps of: (A) Applying at least three successive voltages to the data line. Each respective odd-numbered successive voltage of the at least three successive voltages has substantially a first voltage val...	04/29/2008
7362140	Low swing current mode logic family The present invention provides a low swing current mode logic circuit including: a current mode logic block having data inputs and outputs; a pre-charging circuit for pre-charging the outputs; a dynamic current source; an evaluation circuit for evaluating the logic ...	04/22/2008
7362154	Radiation hardened latch A programmable phase frequency divider for space applications is implemented in CMOS technology, and consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division r...	04/22/2008
7335568	Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, forming a doped region in the bulk substrate under the active layer, forming a plurality of transistors abov...	02/26/2008
7332780	Inverter, semiconductor logic circuit, static random access memory and data latch circuit A dual structure is introduced to the transistor in a flip-flop or a data input step controlled by a clock of a semiconductor logic circuit. The dual structure is formed by connecting a transistor with a MOS transistor having a channel of the same conductivity type ...	02/19/2008
7333380	SRAM memory device with flash clear and corresponding flash clear method A static memory device includes at least one memory cell with two cross-coupled CMOS inverters to be connected to first and second voltages. The substrate of the NMOS transistor of a first CMOS inverter is electrically insulated from the substrate of the NMOS transi...	02/19/2008
7323920	Soft-error rate improvement in a latch using low-pass filtering In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. A low-pass filter is placed between the output of a forward inverter and the inputs of a feedback keeper. The first and second outputs of the low-pass f...	01/29/2008
7319357	System for controlling switch transistor performance The present invention provides a system for controlling performance of a switch transistor (106)—one that is implemented within a circuitry segment (100) to shut off a circuitry component (116) when that component is not in use. The switch tra...	01/15/2008
7301381	Clocked state devices including master-slave terminal transmission gates and methods of operating same A clocked state circuit can include a transmission gate configured to clock an output of a master terminal to an input of a slave terminal responsive to a clock signal or a delayed clock signal coupled to the transmission gate. ...	11/27/2007
7289375	Data holding circuit A data holding circuit includes a first data holding unit, a second data holding unit and a selection unit. In the first data holding unit, a probability of a soft error at a time when input data has a first level is lower than a probability of a soft error at a tim...	10/30/2007
7265589	Independent gate control logic circuitry A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combinatio...	09/04/2007
7265582	Level shifter A level shifter is provided. The level shifter includes a first input transistor, a second input transistor, a first bias transistor, a second bias transistor, a first switch transistor and a second switch transistor. At the time of change of the signal status, by r...	09/04/2007
7259605	Pseudo true single phase clock latch with feedback mechanism A pseudo true single phase clock latch (pseudo “TSPC” latch) includes additional circuitry coupled to three previously floating nodes that can lose data depending upon the amount of leakage current associated with these nodes. The additional circuitry, including...	08/21/2007
7242235	Dual data rate flip-flop A flip-flop is configured to operate either in a double data-rate mode or a normal mode. When configured to operate in the double data-rate mode, the flip-flop outputs data on both edges of the applied clock. When configured to operate in the normal mode, the flip-f...	07/10/2007
7236031	Fast bistable circuit protected against random events A bistable circuit includes a first inverter and a capacitive inversion circuit having one input coupled to an output of the first inverter. The capacitive inversion circuit includes a second inverter and a capacitive circuit parallel-coupled to the input and an out...	06/26/2007
7227808	Semiconductor memory device which compensates for delay time variations of multi-bit data A memory device compensates for delay time variations among multi-bit data. The device includes a first stage and a second stage of data storage units. The first stage of data storage units store first to nth data bits in response to a latch clock signal. The second...	06/05/2007
7224190	Midcycle latch for power saving and switching reduction The present invention relates to the field of hardware logic circuits and in particular to dynamic hardware logic implemented in computer processors, and more particularly, to an integrated circuit comprising a dynamic logic function implementing a predetermined log...	05/29/2007
7218162	Semiconductor integrated circuit having output circuit A semiconductor integrated circuit that has an output circuit in which an output-stage operating voltage lower than a power supply voltage is applied to an output stage is provided. Even when the power supply voltage is lowered, a sufficient output signal amplitude ...	05/15/2007
7218160	Semiconductor integrated circuit A semiconductor integrated circuit according to the present invention comprises a latch circuit, a retaining circuit, and a feedback circuit, wherein the latch circuit inputs therein an input data signal, a clock signal and a feedback signal and outputs an output da...	05/15/2007
7215940	Integrated circuit Embodiments of the present invention relates to an integrated mixer. A problem with producing low power consumption mixers is that they require a relatively high operating voltage due to the number of layers of transistor between the power rails. Accordingly, an emb...	05/08/2007
7215154	Maskable dynamic logic An apparatus and method provide logically controlled masking of one or more maskable data bits from a plurality of data bits that are input to a dynamic logic circuit. No masking logic and attendant delay penalty is coupled in the data path that is not needed for un...	05/08/2007
7215169	Current-controlled CMOS logic family Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, X...	05/08/2007
7212056	Radiation hardened latch A radiation hardened latch is presented. The radiation hardened latch uses two redundant inverter paths to duplicate an input signal. The duplicated inverter paths are coupled with a radiation hardened inverter that will only produce an inverted signal if both input...	05/01/2007
7205810	Skew tolerant phase shift driver with controlled reset pulse width A phase shift driver for phase shifting an input clock signal at a first phase to generate an output signal at a second phase without missing subsequent input signals. Input logic circuitry of the phase shift driver may receive an input signal at a first phase. Outp...	04/17/2007
7202705	Dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control A dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control reduces power consumption of processors and other systems incorporating dynamic circuits. The power control signal may be a delayed versio...	04/10/2007
7202725	Delay control circuit device, and a semiconductor integrated circuit device and a delay control method using said delay control circuit device By forming adjacent wiring 4 adjacent to signal wiring 3 and using a control circuit 13 comprising a 2-input NAND 20 circuit or the like to input a signal S4 corresponding to a signal S3 in the signal wiring 3 to the ...	04/10/2007
7202699	Voltage tolerant input buffer A method and an apparatus are described for a voltage tolerant input buffer. An embodiment of an input buffer includes a differential circuit and a plurality of switches coupled with the differential circuit. The plurality of switches applies a voltage to the differ...	04/10/2007
7193446	Dynamic logic circuit incorporating reduced leakage state-retaining devices A dynamic logic circuit incorporating reduced leakage state-retaining devices reduces power consumption of processors and other systems incorporating dynamic circuits. A keeper circuit provides a low leakage retention of the state of the output stage of the dynamic ...	03/20/2007
7187016	Semiconductor device In a semiconductor device an electric field is controlled in direction or angle relative to a gate, or a channel to adjust a gain coefficient of a transistor. In some embodiments, there are provided a first gate forming a channel region in a rectangle or a parallelo...	03/06/2007
7183812	Stable systems for comparing and converting signals Comparator systems are provided that include cross-coupled transistors which respond to a differential network that receives an input signal. The systems further include a control transistor connected across the cross-coupled transistors and a bias network configure...	02/27/2007
7180973	Programmable low-power high-frequency divider A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to ...	02/20/2007
7173480	Device for controlling the operation of internal voltage generator The present invention discloses a circuit for controlling a timing of overdriving a core voltage (internal voltage) which is a driving voltage of a sense amplifier of a memory device and a duration of the overdriven core voltage, and a method for easily measuring th...	02/06/2007

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Class 327/210 - CMOS