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| Number | Title | Issue Date |
| 7425855 | Set/reset latch with minimum single event upset A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes any L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in... | 09/16/2008 |
| 7319353 | Non-latching enveloping curves generator An enveloping curves generator is disclosed that guarantees that one curve will envelop or overlap another when both are traversing from one logic level to another, and where the other overlaps the first when both traversing the other direction. In one case, a steer... | 01/15/2008 |
| 7265582 | Level shifter A level shifter is provided. The level shifter includes a first input transistor, a second input transistor, a first bias transistor, a second bias transistor, a first switch transistor and a second switch transistor. At the time of change of the signal status, by r... | 09/04/2007 |
| 7002388 | Nonvolatile flip-flop circuit and method of driving the same The present invention provides a method of driving a nonvolatile flip-flop circuit comprising the following steps of: a data hold step of holding an input data signal D utilizing polarization of a ferroelectric material of a ferroelectric gate transistor (601... | 02/21/2006 |
| 6838920 | Enveloping curves generator circuit An enveloping curve generator that guarantees one curve will overlap another when both are going high and the other overlaps the first when both are going low. When the input goes high, one steering FET is turned off and the other directs the input signal to drive a... | 01/04/2005 |
| 6087872 | Dynamic latch circuitry A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop... | 07/11/2000 |
| 6075748 | Address counter cell An address counter cell for use in burst mode operation in a synchronous DRAM is described which, in response to a falling edge of a system clock, simultaneously loads address inputs into an external address master latch and an internal address master lat... | 06/13/2000 |
| 5763960 | Power supply controlled operation sequencing method and apparatus A method and apparatus for sequencing the operation of electronic circuits based upon the level of the voltage provided by an external power supply. One or more power supply sequencer circuits may be interposed between an external power supply and one or ... | 06/09/1998 |
| 5537076 | Negative resistance circuit and inverter circuit including the same A new negative resistance circuit comprises a first N-channel enhancement FET (E-FET), an N-channel depletion FET as a load element connected to the first N-channel E-FET to form a series branch connected between negative resistance ports, and a second N-... | 07/16/1996 |
| 4740714 | Enhancement-depletion CMOS circuit with fixed output In a CMOS FET IC element including at least one pair of transistors with connected drains, one an N-channel MOSFET and one a P-channel MOSFET, the N-channel MOSFET having a first threshold voltage controlled by the implantation of an ion, and the P-channe... | 04/26/1988 |
| 4596938 | Electrically erasable programmable electronic circuits using programmable-threshold-voltage FET pairs The series connection between operating voltage terminals of the channels of field effect transistors with electrically alterable threshold voltage, programmed one for conduction and the other for non-conduction in response to programming voltage on their... | 06/24/1986 |
| 4439691 | Non-inverting shift register stage in MOS technology A non-inverting integrated circuit shift register stage is provided by a combination of four interconnected N-MOS transistors, connected to a two-phase clock pulse voltage source.... | 03/27/1984 |
| 4053873 | Self-isolating cross-coupled sense amplifier latch circuit Disclosed is a self-isolating cross-coupled sense amplifier latch circuit having five enhancement mode field effect transistor devices and two depletion mode field effect transistor devices. The first and second field effect transistors form a cross-coupl... | 10/11/1977 |
| 4006469 | Data storage cell with transistors operating at different threshold voltages A semiconductor memory or storage circuit includes cross coupled transistors and isolating transistors operating at a first threshold voltage and load transistors for the cross coupled transistors operating at a second threshold voltage. The storage cell ... | 02/01/1977 |
| 4004170 | MOSFET latching driver An MOSFET latching driver circuit is disclosed which employs a depletion mode FET load bistable latch whose first node drives a depletion mode FET device and whose second node drives an enhancement mode FET device which are interconnected in a push-pull d... | 01/18/1977 |
