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| Number | Title | Issue Date |
| 8044695 | Semiconductor integrated circuit including a master-slave flip-flop A semiconductor integrated circuit having a flip-flop with improve soft error resistance, including a controller which controls a clock signal generating circuit to output a first clock signal and a second clock signal with a timing so that logic of data retained in... | 10/25/2011 |
| 8013649 | Dynamic clock feedback latch A dynamic clock feedback latch includes a feedback path that generates a data value on an output as a function of data inputs in response to a clock input going low and generates a latching value on the output after a delay from the clock input going high. A first t... | 09/06/2011 |
| 7872513 | Apparatus and circuit including latch circuit, and method of controlling latch circuit An apparatus includes a first selector which selects a test data during a first operation mode, and selects a first input data during a second operation mode, a first latch circuit which latches an output signal of the first selector according to a first clock signa... | 01/18/2011 |
| 7772906 | Low power flip flop through partially gated slave clock A system and method for reducing power consumption within a flip-flop circuit on a semiconductor chip. A gated input clock signal is received by a slave latch. The gated input clock is derived from an ungated input clock signal and a clock gating condition. The cloc... | 08/10/2010 |
| 7746139 | Radiation hardened D-type flip flop A programmable phase frequency divider for space applications is implemented in CMOS technology, and includes a number of radiation hardened D-type flip flops. The radiation hardened D-type flip flop circuits are designed to keep running properly at GHz frequencies ... | 06/29/2010 |
| 7733144 | Radiation hardened CMOS master latch with redundant clock input circuits and design structure therefor A radiation hardened master latch for use in a programmable phase frequency divider operating at GHz frequencies is implemented in deep submicron CMOS technology, and consists of two identical half circuits interconnected in a DICE-type configuration that makes the ... | 06/08/2010 |
| 7688125 | Latched comparator and methods for using such Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with a preamplifier circuit, a latch circuit and a current re-use circuit. The current re-use circuit applies a... | 03/30/2010 |
| 7652513 | Slave latch controlled retention flop with lower leakage and higher performance In a method and apparatus for data retention, a first latch latches a data input and a second latch that is coupled to the first latch retains the data input while the first latch is inoperative in a standby power mode. The second latch includes a second latch inver... | 01/26/2010 |
| 7622976 | Sequential circuit design for radiation hardened multiple voltage integrated circuits The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodimen... | 11/24/2009 |
| 7564282 | Bistable flip-flop having retention circuit for storing state in inactive mode A bistable flip-flop device is provided that is triggered on the edges of a clock signal. The device has an active mode in which it is electrically powered and an inactive mode. The device includes a chain of inverters controlled by a clock signal, storage means for... | 07/21/2009 |
| 7492202 | Flip-flop circuit To keep input capacitance and driving capability at respective data input and output terminals of a flip-flop circuit, the flip-flop includes: a master latch portion; a slave latch portion; and a data output selecting portion. The master latch portion includes a tri... | 02/17/2009 |
| 7440534 | Master-slave flip-flop, trigger flip-flop and counter A master latch (1) is formed from a static circuit, and a slave latch (2) is formed from a dynamic circuit. The number of circuit elements can be smaller as compared to a slave latch formed from a static circuit so that the size and area of a master-sl... | 10/21/2008 |
| 7427875 | Flip-flop circuit Signal delivery delay margin of a bypass flip-flop circuit is stabilized during high-frequency operation. An input controller for logically operating a bypass signal and a clock produces first and second output signals having different states depending on whether or... | 09/23/2008 |
| 7425855 | Set/reset latch with minimum single event upset A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes any L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in... | 09/16/2008 |
| 7405605 | Storage elements using nanotube switching elements Data storage circuits and components of such circuits constructed using nanotube switching elements. The storage circuits may be stand-alone devices or cells incorporated into other devices or circuits. The data storage circuits include or can be used in latches, ma... | 07/29/2008 |
| 7405606 | D flip-flop A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback ele... | 07/29/2008 |
| 7391249 | Multi-threshold CMOS latch circuit Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal... | 06/24/2008 |
| 7391250 | Data retention cell and data retention method based on clock-gating and feedback mechanism For retaining an output data signal of a data retention cell in a power-saving mode, a slave latch unit of the data retention cell is powered with a real power for preserving the output data signal. The output data signal is furnished backward to an input control ci... | 06/24/2008 |
| 7388416 | Latch circuit, 4-phase clock generator, and receiving circuit A latch circuit includes a voltage driven type data reading unit and a voltage driven type data holding unit, and operates based on a clock signal that is supplied from an outside source. The data reading unit reads both a first input data and a second input data, a... | 06/17/2008 |
| 7378890 | Programmable low-power high-frequency divider Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also describ... | 05/27/2008 |
| 7379491 | Flop repeater circuit A system is provided that includes a clocking circuit to provide two repeater clock signals and a flop repeater circuit to receive the two repeater clock signals and an input data signal. The flop repeater circuit to provide an output data signal based on the two re... | 05/27/2008 |
| 7378869 | Lookup table circuits programmable to implement flip-flops A lookup table (LUT) is programmable to function as a flip-flop. The LUT includes a plurality of memory cells, a plurality of transmission gates, and first and second logic gates. The transmission gates are coupled between the memory cells and an output terminal of ... | 05/27/2008 |
| 7375567 | Digital storage element architecture comprising dual scan clocks and preset functionality A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first tran... | 05/20/2008 |
| 7365596 | State retention within a data processing system Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when ... | 04/29/2008 |
| 7365576 | Binary digital latches not using only NAND or NOR circuits A switching model to create stable binary sequential devices comprised of one or more logic functions with feedback of which an output signal is uniquely related to an input signal is applied to possible binary logic functions. Static latches of commutative and non-... | 04/29/2008 |
| 7362154 | Radiation hardened latch A programmable phase frequency divider for space applications is implemented in CMOS technology, and consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division r... | 04/22/2008 |
| 7358787 | Dual operational mode CML latch A dual purpose current mode logic (“CML”) latch circuit is provided which includes a CML latch operable to receive at least a pair of differential input data signals and at least one clock signal. The CML latch is operable to generate at least one output signal ... | 04/15/2008 |
| 7345518 | Digital storage element with dual behavior A digital storage element comprises a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedi... | 03/18/2008 |
| 7342429 | Programmable low-power high-frequency divider Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also describ... | 03/11/2008 |
| 7332949 | High speed pulse based flip-flop with a scan function and a data retention function Provided is a multi-threshold CMOS (MTCMOS) flip-flop for latching a data input signal in response to a clock signal and converting the latched signal to a data output signal. The flip-flop includes: a latch unit receiving the data input signal in a normal mode, lat... | 02/19/2008 |
| 7327169 | Clocked inverter, NAND, NOR and shift register A threshold voltage of a transistor is fluctuated because of fluctuation in film thickness of a gate insulating film or in gate length and gate width caused by differences of used substrates or manufacturing steps. In order to solve the problem, according to the pre... | 02/05/2008 |
| 7323911 | Differential sense amplifier circuit and method triggered by a clock signal through a switch circuit A differential sense amplifier is described that can be configured as a preamplifier or a latch circuit as triggered by a clock signal connected to a switch circuit. When the clock signal is set at a first signal level, the switch circuit in the differential sense a... | 01/29/2008 |
| 7321506 | Multivibrator protected against current or voltage spikes The multivibrator is protected against current or voltage spikes and includes a first data transfer port that receives, as input, multivibrator input data, and a first/master latch cell connected on the output side of the first transfer port. A second/slave latch ce... | 01/22/2008 |
| 7315191 | Digital storage element architecture comprising dual scan clocks and reset functionality A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first tran... | 01/01/2008 |
| 7313178 | Transceiver for receiving and transmitting data over a network and method for testing the same The present invention provides a transceiver for receiving and transmitting data over a network, and a method for testing the same. In particular, the present invention provides a physical layer transceiver having a built-in-self-test (BIST) device that allows for, ... | 12/25/2007 |
| 7304518 | Track and hold circuit A track and hold circuit (1) comprising:—a linear amplifier (2) receiving a differential analog signal (D+, D−) and being controlled by a first binary clock signal (H+) having a first phase,—the linear amplifier (2) providing a feed-forwar... | 12/04/2007 |
| 7304519 | Data latch, master/slave flipflop and frequency divider circuit A data latch contains a supply connection, a reference ground potential connection and a data input. The input side of an inverter is connected to the data input, and it is coupled via a first switching device to the supply connection, and via a second switching dev... | 12/04/2007 |
| 7301381 | Clocked state devices including master-slave terminal transmission gates and methods of operating same A clocked state circuit can include a transmission gate configured to clock an output of a master terminal to an input of a slave terminal responsive to a clock signal or a delayed clock signal coupled to the transmission gate. ... | 11/27/2007 |
| 7292482 | Multivibrator protected against current or voltage spikes A multivibrator circuit includes a first data transfer port that receives, as input, multivibrator input data, a first, master, latch cell connected on the output side of the first transfer port, a second, slave, latch cell, and a second data transfer port placed be... | 11/06/2007 |
| 7292672 | Register circuit, and synchronous integrated circuit that includes a register circuit A register circuit includes a passage control circuit and a holding circuit. The passage control circuit includes a first transistor having a gate to which a clock signal is input, a second transistor having a gate to which a data signal is input, and a third transi... | 11/06/2007 |
