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| Number | Title | Issue Date |
| 8063685 | Pulsed flip-flop circuit A flip-flop circuit includes a data input, a clock input for receiving a clock signal having active edges and inactive edges, a data output, an input circuit, a pulse generator, and a latch. The input circuit sets first and second nodes to different initial logic st... | 11/22/2011 |
| 8044694 | Semiconductor integrated circuit having latch circuit applied changeable capacitance and method thereof A semiconductor integrated circuit includes a flip-flop circuit, a capacitive element, and a switch circuit. The switch circuit includes a first switch circuit which couples the capacitive element to two nodes of the flip-flop circuit at a first timing, and a second... | 10/25/2011 |
| 7768330 | Logic circuit For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an “H” level and a latch par... | 08/03/2010 |
| 7427875 | Flip-flop circuit Signal delivery delay margin of a bypass flip-flop circuit is stabilized during high-frequency operation. An input controller for logically operating a bypass signal and a clock produces first and second output signals having different states depending on whether or... | 09/23/2008 |
| 7388416 | Latch circuit, 4-phase clock generator, and receiving circuit A latch circuit includes a voltage driven type data reading unit and a voltage driven type data holding unit, and operates based on a clock signal that is supplied from an outside source. The data reading unit reads both a first input data and a second input data, a... | 06/17/2008 |
| 7382161 | Accelerated P-channel dynamic register A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal, and opens an evaluation window when the pulsed clock signal goes low,... | 06/03/2008 |
| 7362154 | Radiation hardened latch A programmable phase frequency divider for space applications is implemented in CMOS technology, and consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division r... | 04/22/2008 |
| 7348806 | Accelerated N-channel dynamic register A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal, and opens an evaluation window when the pulsed clock signal goes high... | 03/25/2008 |
| 7323920 | Soft-error rate improvement in a latch using low-pass filtering In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. A low-pass filter is placed between the output of a forward inverter and the inputs of a feedback keeper. The first and second outputs of the low-pass f... | 01/29/2008 |
| 7301381 | Clocked state devices including master-slave terminal transmission gates and methods of operating same A clocked state circuit can include a transmission gate configured to clock an output of a master terminal to an input of a slave terminal responsive to a clock signal or a delayed clock signal coupled to the transmission gate. ... | 11/27/2007 |
| 7276958 | Charge pump with reduced noise spikes A voltage supply circuit which suppresses generation of current spikes in the power source current in operation, reduce noise, simplify the circuit configuration, and decrease the cost. Clock signal CLK at a prescribed frequency is supplied to charge pump driver ( | 10/02/2007 |
| 7274221 | Comparator circuit An improved comparator circuit and associated methods are disclosed. In one embodiment, the comparator circuit comprises two voltage-to-time converter circuits, one for each input voltage to be compared, and an arbiter circuit for receiving the time-converted output... | 09/25/2007 |
| 7236032 | Ultra-drowsy circuit Method and apparatus for an ultra-drowsy circuit for use in lower power operational modes are described. ... | 06/26/2007 |
| 7233184 | Method and apparatus for a configurable latch A configurable latch comprises a dual master stages arranged in parallel to share a single output node. The configurable latch provides a single slave stage at the single output node to be shared between the two master stages. Pass gates controlled by various phases... | 06/19/2007 |
| 7215155 | Control circuits and methods including delay times for multi-threshold CMOS devices Multi-Threshold CMOS (MTCMOS) devices include a high threshold voltage current control switch that is responsive to a first control signal, a low threshold voltage logic circuit and a flip-flop that is configured to store data from the low threshold voltage logic ci... | 05/08/2007 |
| 7205986 | Image display device and testing method of the same It is the primary object of the present invention to provide a simple and accurate testing circuit and a testing method while occupying as small space as possible in an image display device. The testing circuit including a NAND circuit connected in series is mounted... | 04/17/2007 |
| 7187204 | Circuit for inspecting semiconductor device and inspecting method It is configured by plurality of NAND circuits connected in series through a plurality of inverters, and a plurality of NOR circuits connected in series through the plurality of inverters. Each of a plurality of source signal lines provided in a pixel portion is con... | 03/06/2007 |
| 7180349 | Frequency divider system A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which op... | 02/20/2007 |
| 7180348 | Circuit and method for storing data in operational and sleep modes The application relates to a circuit for storing a signal during sleep mode, said embodiments of the circuit comprising: a sleep signal input operable to receive a sleep signal; a clock signal input operable to receive a clock signal; a plurality of latches clocked ... | 02/20/2007 |
| 7180973 | Programmable low-power high-frequency divider A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to ... | 02/20/2007 |
| 7176736 | High-speed, current driven latch A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the ... | 02/13/2007 |
| 7173456 | Dynamic logic return-to-zero latching mechanism A dynamic logic return-to-zero (RTZ) latching mechanism including a complementary pair of evaluation devices responsive to a clock signal, a dynamic evaluator, delayed inversion logic, and latching logic. The dynamic evaluator is coupled between the complementary pa... | 02/06/2007 |
| 7173465 | High-speed, current-driven latch A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the ... | 02/06/2007 |
| 7164302 | One gate delay output noise insensitive latch A one gate delay output noise insensitive latch includes an input node, an output node, a storage node, a not storage node, and a data clock line. A primary latch element is connected to the input node, the output node, and the data clock line. A mirror primary latc... | 01/16/2007 |
| 7145365 | Logic processing apparatus, semiconductor device and logic circuit Off-leak electric current is reduced in the operation mode where a circuit is actually operating. In the state in which the power supply voltage is constantly applied to the front stage flip-flops 11 to 13 and rear stage flip-flops 21 to ... | 12/05/2006 |
| 7132856 | Hybrid CVSL pass-gate level-converting sequential circuit for multi-Vcc microprocessors A logic circuit performs an internal level conversion function by driving portions of the circuit with different supply voltages. In one embodiment, first and second stage storage circuits are driven with different supply voltages. In another embodiment, first and s... | 11/07/2006 |
| 7109749 | Programmable logic devices providing reduced power consumption A Programmable Logic Device providing reduction in power consumption for sequential logic and data storage functions, including at least one circuit arrangement configurable to function as a dual-edge-triggered flip-flop operating on a selected one or both edges of ... | 09/19/2006 |
| 7102406 | Phase detector, clock distribution circuit, and LSI A phase detector includes a first selection circuit configured to select a first clock from a first group of clocks supplied to the first selection circuit and to transmit the first clock, and at least one phase comparator configured to detect a difference in phases... | 09/05/2006 |
| 7098695 | Dynamic-to-static logic converter This disclosure is directed to techniques for reducing erroneous static logic signals when logic signals change relative to a clock signal within a dynamic to static logic converter circuit. Domino logic circuits, for example, utilize dynamic logic signals evaluated... | 08/29/2006 |
| 7084683 | High-speed differential flip-flop with common-mode stabilization A differential flip-flop (400) has an output stage (402) with first and second input terminals (X1, X2), first and second output terminals (Q, Qb), a first voltage supply terminal (Vss), a first transistor (435) having a first curr... | 08/01/2006 |
| 7075350 | Programmable low-power high-frequency divider A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to ... | 07/11/2006 |
| 7046063 | Interface circuit for coupling between logic circuit domains CMOS circuitry is partitioned into first and second logic circuit domains. The first logic circuit domain may be optionally a cuttable domains (C_Domains) where circuitry has power supply gating to reduce leakage power and non-cuttable domains (NC_Domains) where cir... | 05/16/2006 |
| 7030672 | Adiabatic charging register circuit An adiabatic charging register circuit comprising a plurality of n-channel MOSFET's and a plurality of p-channel MOSFET's, is operated by a clock signal which has a gradually rising and a gradually falling waveform generated by using a charge recycle power source in... | 04/18/2006 |
| 7023255 | Latch with data jitter free clock load A digital latch includes a latch circuit having first and second data inputs, first and second data outputs, and a clock signal input. The latch circuit has a first load value relative to a clock driver when data at the first and second data inputs is non-changing. ... | 04/04/2006 |
| 7009438 | Trans-admittance trans-impedance logic for integrated circuits A logic circuit with improved performance when operating at the limits of the transistor's bandwidth. In particular, a latch includes a clocked trans-admittance stage circuit for receiving a voltage and producing a current output, and an active load, such as a trans... | 03/07/2006 |
| 7005893 | High-performance clock-powered logic High performance clock-powered logic runs at below supply levels and reduces the need for faster digital logic circuitry. In a preferred embodiment, a clocked buffer (101) is used to drive the signal line. The receiving end of the line is connected to a jam l... | 02/28/2006 |
| 7003049 | Fractional-N digital modulation with analog IQ interface Digital I and Q (NRZ) data streams are generated by specially configured conversion circuits, the outputs of which are applied to a F-N synthesizer to modulate the synthesizer. All illustrative conversion circuit employs a system of comparators to detect the state o... | 02/21/2006 |
| 6965254 | Dynamic logic register A dynamic logic register including a dynamic circuit, a delayed inverter, a latching circuit, and a keeper circuit. The dynamic circuit pre-charges a pre-charged node while a clock signal is low and evaluates a logic function to control the state of the pre-charged ... | 11/15/2005 |
| 6956421 | Slave-less edge-triggered flip-flop An edge-triggered flip flop includes a clocking portion having first and second transistor stacks that are coupled to first and second storage nodes of a memory element, respectively. In at least one embodiment, a clock signal is applied to an input of at least one ... | 10/18/2005 |
| 6946878 | Integrated circuit and circuit arrangement for converting a single-rail signal into a dual-rail signal An integrated circuit that converts a single rail signal into a dual-rail signal includes a clock signal connection, a data input to which a single-rail signal is applied, a data output on which a dual-rail signal is tapped off on output lines, and a converter, whic... | 09/20/2005 |
