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| Number | Title | Issue Date |
| 7414438 | Clock based voltage deviation detector The clock based voltage deviation detector of the present invention includes a pulse module, an indicator module and a correlation module. The pulse module generates a stream of reset pulses as a function of a clock signal. The indicator module generates a pass/fail... | 08/19/2008 |
| 7383370 | Arbiter circuit and signal arbitration method An arbiter circuit (100) can include a latch circuit (102) that latches competing input signals (MATCH1 and MATCH2) to generate signals on latch output (110-0 and 110-1). A filter section (104) can preve... | 06/03/2008 |
| 7366244 | Method and system for antenna interference cancellation A wireless communication system can comprise two or more antennas that interfere with one another via free space coupling, surface wave crosstalk, dielectric leakage, or other interference effect. The interference effect can produce an interference signal on one of ... | 04/29/2008 |
| 7362134 | Circuit and method for latch bypass A device includes a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypa... | 04/22/2008 |
| 7312627 | Decoding circuit for on die termination in semiconductor memory device and its method A decoding circuit of an on die termination (ODT) control signal for stably performing an ODT operation. The decoding circuit includes: a latch unit for receiving a plurality of input signals and for holding previous output signals of the latch unit when the plurali... | 12/25/2007 |
| 7274221 | Comparator circuit An improved comparator circuit and associated methods are disclosed. In one embodiment, the comparator circuit comprises two voltage-to-time converter circuits, one for each input voltage to be compared, and an arbiter circuit for receiving the time-converted output... | 09/25/2007 |
| 7237213 | Process and device for timing analysis of a circuit Circuit elements are operated as a function of a state of at least one change-over signal, in each case with a particular respective clock mode. Timing analysis is carried out by means of a description of the circuit. The description contains information as to wheth... | 06/26/2007 |
| 7225283 | Asynchronous arbiter with bounded resolution time and predictable output state An arbiter circuit (100) can include a latch (106) that latches competing input signals (Req_A and Req_B) to generate latch output signals (latn1 and latn2). A filter section (108) can prevent metastable states of latch output sign... | 05/29/2007 |
| 7209065 | Rotary flash ADC A system and method for converting an analog signal to a digital signal is disclosed. The system includes a multiphase oscillator preferable a rotary oscillator, a sample and hold circuit, an integrator and a time-to-digital converter. The multiphase oscillator has ... | 04/24/2007 |
| 7123676 | Method and system for antenna interference cancellation A wireless communication system can comprise two or more antennas that interfere with one another via free space coupling, surface wave crosstalk, dielectric leakage, or other interference effect. The interference effect can produce an interference signal on one of ... | 10/17/2006 |
| 7064583 | Arbiters with preferential enables for asynchronous circuits One embodiment of the present invention provides a circuit that preferentially grants requests. This circuit monitors at least two inputs for request signals and at least two inputs for enable signals, wherein each request signal is associated with a corresponding e... | 06/20/2006 |
| 7061282 | Differential signal pairs generator A device for generating a pair of true/complementary-phase logic signals is provided. The device comprises a single-end to true/complementary-phase signal conversion circuit, a first stage circuit and a differential amplifier. The conversion circuit receives a singl... | 06/13/2006 |
| 7050388 | Method and system for crosstalk cancellation Signals propagating in one communication channel can generate crosstalk interference in another communication channel. A crosstalk cancellation device can process the signals causing the crosstalk interference and generate a crosstalk cancellation signal that can co... | 05/23/2006 |
| 7039824 | Calibrating return time with cross-coupled arbiter/delay circuits to compare clock signals Calibrating return time includes determining clock calibration information based on clock signals local to a master device and return clock signals corresponding to each of at least two slave devices, storing clock calibration information with respect to each of the... | 05/02/2006 |
| 6963969 | Method and processor for initializing a plurality of non-overlapping areas with associated flags and signals The processor includes the first through third areas which can be initialized based on an input of the PRST signal. The second and third areas can be initialized based on an input of the HRST signal. The third area can be initialized based on an input of the SRST si... | 11/08/2005 |
| 6960926 | Method and apparatus for characterizing a circuit with multiple inputs A method of characterizing a circuit comprises the steps of measuring a first delay associated with the circuit when the circuit is substantially unloaded; measuring a second delay associated with the circuit when the circuit is loaded by a predetermined impedance; ... | 11/01/2005 |
| 6956188 | Induction heating coil with integrated resonant capacitor and method of fabrication thereof, and induction heating system employing the same An induction heating coil with integrated resonant capacitor is provided, along with methods of fabrication thereof, and induction heating systems employing the same. The induction heating coil includes a cable having a first conductor and a second conductor separat... | 10/18/2005 |
| 6781418 | Arbiter/pulse discriminator circuits with improved metastable failure rate by delayed balance point adjustment An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to arbitrate a plurality of input request signals and present one or more first control signals. The second circuit may be configured to control the arbitration in resp... | 08/24/2004 |
| 6774679 | Semiconductor integrated circuit In a semiconductor integrated circuit including a phase comparator circuit for a PLL or DLL, overall lock precision of the PLL or DLL is improved by eliminating a dead zone of the phase comparator circuit and preventing output current offset of a charge pump circuit... | 08/10/2004 |
| 6617900 | Arbitrator with no metastable voltage levels on output An arbiter that includes a phase comparator receiving two input signals. The outputs of the phase comparator are propagated to a first SR type flip-flop. The outputs of the first SR type flip-flop are propagated to a second SR type flip-flop. The outputs ... | 09/09/2003 |
| 6340901 | Measurement of signal propagation delay using arbiters Arbiter circuits placed between two signal path segments on a semiconductor chip to measure the difference in propagation delay between those paths at their beginning and end. Each arbiter circuit has two inputs, and outputs signals indicating which of it... | 01/22/2002 |
| 6188249 | Asymmetric arbiter with fast signal path An asymmetric arbiter provides a fast signal path and a slow signal path. Signals may travel over the fast signal path in substantially less time than it takes for the signals to travel over the slow signal path. The fast signal path may be configured so ... | 02/13/2001 |
| 6111436 | Measurement of signal propagation delay using arbiters Arbiter circuits placed between two signal path segments on a semiconductor chip to measure the difference in propagation delay between those paths at their beginning and end. Each arbiter circuit has two inputs, and outputs signals indicating which of it... | 08/29/2000 |
| 6002274 | Oversampled state machine for jitter tolerant pulse detection A transmission line sampling circuit for a T1 line is disclosed. A multi phase oscillator is connected to a plurality of state machines which are connected in parallel to a transmission line. The use of a plurality of state machines to sample the transmis... | 12/14/1999 |
| 5896048 | Method for determining active/stand-by mode for use in a duplicated system An active/stand-by determination method for use in a duplicated system, wherein two elements, one given a priority and the other not given a priority, in the duplicated system operate in an active mode and a stand-by mode alternatively by using an X-... | 04/20/1999 |
| 5838171 | Low power real-time clock circuit having system and battery power arbitration A circuit for power arbitration, low battery voltage detection, and the operation of battery backed circuitry for systems in which the system power supply voltage range overlaps that of a battery source. A voltage regulator is used to regulate the battery... | 11/17/1998 |
| 5825211 | Oversampled state machine for jitter tolerant pulse detection A transmission line sampling circuit for a T1 line is disclosed. A multi phase oscillator is connected to a plurality of state machines which are connected in parallel to a transmission line. The use of a plurality of state machines to sample the transmis... | 10/20/1998 |
| 5714901 | Hysteretic coupling system An interconnecting network comprising operational amplifiers, summing ampiers, and hysteretic coupling circuits is disclosed. The interconnecting network responds to signals of interest that may be substantially simultaneously present, but only to the hi... | 02/03/1998 |
| 5568072 | Circuit indicating the phase relation between several signals having the same frequency A circuit, indicating the first or last signal activated among n signals, includes flip-flops respectively associated with pairs of signals, a first signal of each pair being applied to a reset input of a flip-flop and a second signal of each pair being a... | 10/22/1996 |
| 5555540 | ASIC bus structure A bi-directional ring bus structure is formed on an integrated circuit from a conductive bus and M X:1 multiplexer modules (where M is an integer ࣙ2), coupled in a point-to-point configuration. Each module is associated with an input/output port that ca... | 09/10/1996 |
| 5539338 | Input or output selectable circuit pin A circuit for selecting between two states and using the same pin as an input and an output. On power-up, the pin can be connected to either a grounded resistor (to select the first state) or the power supply (to select the second state). The input signal... | 07/23/1996 |
| 5495190 | Arbiter circuit An arbiter circuit for determining priority as between two or more competing request signals and applicable for use in a memory system having a number of memories operating independently without interfering with one another. For each of a number of memori... | 02/27/1996 |
| 5341052 | Arbiter with test capability and associated testing method An arbiter based on pairwise mutual exclusion produces an absolute priority signal (G) indicating that one of three or more requests (R1, R2, . . . RN) has gained absolute priority over all the other. At least one mutual-e... | 08/23/1994 |
| 5315184 | Self arbitrating auto resettable flag circuit A flag setting, reading and clearing circuit is described which includes self arbitrating logic to provide priority for the flag setting portion of the circuit over the flag clearing portion. The flag is set by a set flag signal generated by a portion of ... | 05/24/1994 |
| 5266844 | Timing discriminator circuit and method for determining the arrival order of input signals The present invention is directed to systems and methods capable of analyzing a wide variety of input signal waveforms to arbitrate their arrival sequence with a high resolution. In an exemplary embodiment, the apparatus is an arbiter circuit which includ... | 11/30/1993 |
| 5148112 | Efficient arbiter A logic circuit for use as an arbiter to arbitrate among N devices of a computer system for access to a shared resource. The arbiter generates state variables to represent arbitration win information. The state variables are generated through the use of r... | 09/15/1992 |
| 5136180 | Variable frequency clock for a computer system A circuit generates a system clock signal. On a first input of the circuit a first oscillating signal is placed. On a second input, a second oscillating signal may be placed. Clock sense logic is connected to the second input. The clock sense logic detect... | 08/04/1992 |
| 5121413 | Digital pulse processor for determining leading and trailing time-of-arrival A Digital Pulse Processor (DPP) designed to accept pulsed inputs and produce digital pulse descriptor word (PDW) outputs accepts pulsed signals from three adjacent channelized inputs. The DPP then derives a measurement of pulse amplitude from the peak val... | 06/09/1992 |
| 5065052 | Arbiter circuit using plural-reset RS flip-flops This invention is realized, in sum, by providing at least one reset input terminal, aside from a reset input terminal to which a request end signal is supplied, to output stage RS flip-flops of plural latch circuits to which plural request signals are sup... | 11/12/1991 |
| 5049766 | Delay measuring circuit In a delay measuring circuit (10), an input clock signal (13) is applied to a multitapped delay line (14), the output taps of which are connected to a switch (26) which selects one of the switch inputs for connection to a phase comparator (34) which compa... | 09/17/1991 |
