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| Number | Title | Issue Date |
| 8063683 | Low power clock and data recovery phase interpolator A phase interpolator is provided. The phase interpolator comprises a plurality of reference stages, the reference stages receiving a reference signal having a predetermined phase and outputting a component signal, wherein the reference stages comprise a plurality of... | 11/22/2011 |
| 8054118 | System and method System and method, including path sections, each path section including a supply line into which a medium-frequency current is able to be injected by an infeed assigned to the particular path section, each infeed encompassing a control circ... | 11/08/2011 |
| 8040170 | Semiconductor integrated circuit During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a r... | 10/18/2011 |
| 8013647 | Physical quantity detection circuit and physical quantity sensor device A physical quantity detection circuit (12) is used for a physical quantity sensor (10) that outputs a sensor signal according to a physical quantity given externally. A phase adjustment circuit (100) receives a reference clock (CKref) and operat... | 09/06/2011 |
| 7880520 | Semiconductor integrated circuit During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a r... | 02/01/2011 |
| 7586348 | Systems, apparatuses and methods for synchronizing clock signals An apparatus may include a first phase control circuit and/or a second phase control circuit. The first phase control circuit may compare the phase of the first clock signal with the phase of the second clock signal, and may control the phase of the first clock sign... | 09/08/2009 |
| 7421606 | DLL phase detection using advanced phase equalization A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an On1x ... | 09/02/2008 |
| 7405494 | AC power supply apparatus, methods and computer program products using PWM synchronization Paralleled uninterruptible power supplies (UPSs) including respective pulse-width modulation (PWM) power converter circuits coupled in common to an AC load bus have PWM cycles that are synchronized. In particular, sampling of control inputs of the PWM power converte... | 07/29/2008 |
| 7400182 | Clock generator with one pole and method for generating a clock A clock generator based on a phase-locked loop with one pole and an improved period jitter characteristic is disclosed. The clock generator comprises a phase detector for generating a phase detection signal and a phase error signal, a charge pump for generating a lo... | 07/15/2008 |
| 7397289 | Skew adjusting method, skew adjusting apparatus, and test apparatus There is provided a skew adjusting apparatus for adjusting a skew between a positive-side differential signal and a negative-side differential signal in differential signals inputted from an outside device via outside transmission lines, having a positive-side trans... | 07/08/2008 |
| 7368963 | Delay locked loop for use in semiconductor memory device and method thereof A delay locked loop (DLL) for generating a delay locked clock signal includes a delay line unit for delaying an external clock signal according to a delay amount control signal to thereby generate the delay locked clock signal; a divider for dividing the delay locke... | 05/06/2008 |
| 7362150 | Method and system for synchronizing phase of triangular signal A multiplicity of electronic devices is provided to generate triangular wave signals variable between an upper and lower limit voltages by charging or discharging capacitors. One of the triangular wave signals serves as a master triangular wave signal for controllin... | 04/22/2008 |
| 7352708 | Method and apparatus for border node behavior on a full-duplex bus A method and apparatus relating to the behavior of border nodes within a high performance serial bus system is disclosed. A method for determining and communicating the existence of a hybrid bus is disclosed. A method for determining a path to a senior border... | 04/01/2008 |
| 7353322 | System and method for providing dynamic configuration ROM using double image buffers A dynamic configuration ROM which may be updated while linked to the serial bus and with little or no risk of publishing inconsistent configuration ROM information to the other nodes on the bus. The dynamic configuration ROM comprises first and second configuration ... | 04/01/2008 |
| 7353284 | Synchronized transmission of audio and video data from a computer to a client via an interface A method for controlling data transmission between a computer and a video client via an interface, the method comprising: the computer polling the interface a first time to determine the size of the buffer on the interface; receiving a first buffer size value from t... | 04/01/2008 |
| 7336748 | DDS circuit with arbitrary frequency control clock A test system using direct digital synthesis for generation of a spectrally pure, agile clock. The clock is used in analog and digital instruments in automatic test system. A DDS circuit is synchronized to the tester system clock because it is clocked by a DDS clock... | 02/26/2008 |
| 7330060 | Method and apparatus for sigma-delta delay control in a delay-locked-loop Methods and apparatus are provided for sigma-delta delay control in a Delay-Locked-Loop that employs a delay line to generate a clock signal based on a reference signal. A first value is generated if a clock signal has a time lead relative to a reference signal; and... | 02/12/2008 |
| 7323917 | Method and apparatus for synthesizing a clock signal having a frequency near the frequency of a source clock signal An apparatus and method of synthesizing an output clock signal from a source clock signal. The clock synthesizer includes a phase generator, a phase selector, a phase interpolator, and control circuitry for controlling the phase selector/interpolator. The phase gene... | 01/29/2008 |
| 7319349 | Semiconductor integrated circuit A phase adjustment unit adjusts the phases of a plurality of external clocks successively shifted in phase, thereby generating a plurality of internal clocks having an equal phase difference between every adjacent transition edges thereof. The internal clocks are sy... | 01/15/2008 |
| 7317694 | Method and apparatus for border node behavior on a full-duplex bus A method is disclosed for determining and communicating the existence of a hybrid bus. The method comprises the acts of determining whether the node has a connection to a Legacy link layer; if the node determines that it has a connection to a Legacy link layer, then... | 01/08/2008 |
| 7317362 | Oscillator circuit and oscillation control method An oscillator circuit is disclosed that includes a first oscillation part configured to output a first oscillation output by charging and discharging a first capacitor, and a second oscillation part configured to output a second oscillation output by charging and di... | 01/08/2008 |
| 7310010 | Duty cycle corrector A duty cycle corrector includes a first controllable delay, a second controllable delay, a phase detector, and a compensation circuit. The first controllable delay is configured to delay a first signal to provide a second signal. The second controllable delay is con... | 12/18/2007 |
| 7310262 | Ferroelectric memory capable of continuously fast transferring data words in a pipeline A storage device including a ferroelectric memory cell array including a plurality of memory cells; sense amplifiers connected to the bit lines and selected by a column address; an internal counter able to generate the column address; and a control part controlling ... | 12/18/2007 |
| 7310389 | Method and apparatus for determining the errors of a multi-valued data signal that are outside the limits of an eye mask Disclosed herein is a method and apparatus used to measure the number of time a multi-valued data signal transmitted from either a communication device of subsystem deviates across and into one or more bounded areas or zones as defined by an eye mask that is overlai... | 12/18/2007 |
| 7307460 | Method and apparatus for capacitance multiplication within a phase locked loop A method and apparatus for capacitance multiplication using two charge pumps. A first charge pump (206) provides a current signal (I216) that is first conducted by a resistor (310) of an RC network and then split into three current paths pri... | 12/11/2007 |
| 7304516 | Method and apparatus for digital phase generation for high frequency clock applications An apparatus and method for generating phase-related clocks are disclosed. A clock input is delayed by an alignment magnitude to generate a first phase signal. The first phase signal is delayed by the phase alignment magnitude to generate a first phase delay signal.... | 12/04/2007 |
| 7295053 | Delay-locked loop circuits A delay-locked loop (DLL) circuit comprises a voltage controlled delay line (VCDL) including a plurality of identical delay stages connected in series, and a feedback loop including a phase comparator for controlling the VCDL such that the total delay over a number ... | 11/13/2007 |
| 7280490 | Method and apparatus for border node behavior on a full-duplex bus A method and apparatus relating to the behavior of border nodes within a high performance serial bus system is disclosed. A method is disclosed for determining a path to a senior border during the Self-ID process in a full-duplex communications system having at leas... | 10/09/2007 |
| 7280491 | Method and apparatus for border node behavior on a full-duplex bus A method relating to the behavior of border nodes within a high performance serial bus system is disclosed. A method is disclosed for determining a path to a senior border node comprising the acts of: determining whether a B PHY has received a Self-ID packet without... | 10/09/2007 |
| 7266617 | Method and apparatus for border node behavior on a full-duplex bus A method for determining and communicating the existence of a hybrid bus is disclosed. The method determines whether a connected node is a border node and forwards isochronous and asynchronous requests if the node is not a border node. If the node is a border node, ... | 09/04/2007 |
| 7262645 | System and method for adjusting the phase of a frequency-locked clock A clock signal regeneration system and method to adjust the phase of a frequency-locked clock signal is provided. The system includes a numerically controlled oscillator, a clock source, and an adder. In one embodiment, additional components are included in the syst... | 08/28/2007 |
| 7259599 | Semiconductor device In a semiconductor device of the present invention, a clock is not changed instantaneously but it is changed over maximum N+1/M clocks (N: integer not less than 2) by shifting delay cells in a step by step manner to make the phase state of a previous reference signa... | 08/21/2007 |
| 7237135 | Cyclemaster synchronization in a distributed bridge A method of synchronizing cyclemasters over a distributed bridge is disclosed. The method comprises: a local portal sending a synchronization signal to a peer portal through a bridge fabric upon occurrence of a cycle synchronization event on the local portal; the pe... | 06/26/2007 |
| 7231561 | Apparatus and method for data pattern alignment A digital tester includes a digital data pattern aligner. The digital data pattern aligner includes an alignment pattern source, a data shifter, and a data comparator. The alignment pattern source sends an alignment pattern to the comparator in a data stream. The co... | 06/12/2007 |
| 7224196 | Method and system for synchronizing phase of triangular signal A multiplicity of electronic devices is provided to generate triangular wave signals variable between an upper and lower limit voltages by charging or discharging capacitors. One of the triangular wave signals serves as a master triangular wave signal for controllin... | 05/29/2007 |
| 7212055 | Open-loop digital duty cycle correction circuit without DLL The present invention relates to a semiconductor circuit; and, more particularly, to a duty cycle correction circuit (hereinafter referred to as “DCC”). Furthermore, the present invention relates to an open-loop digital DCC. The duty cycle correction circuit acc... | 05/01/2007 |
| 7199778 | Active matrix display and switching signal generator of same A switching signal generator of an active matrix display is disclosed. The switching signal generator includes at least one delay device connected to the switches of the active matrix display. The delay device consists of many delay units connected in series for rec... | 04/03/2007 |
| 7194650 | System and method for synchronizing multiple synchronizer controllers A system and method for coordinating synchronizer controllers disposed in different clock domains, e.g., a core clock domain and a bus clock domain, wherein a clock synchronizer arrangement is employed for effectuating data transfer across a clock boundary therebetw... | 03/20/2007 |
| 7194564 | Method and apparatus for preventing loops in a full-duplex bus A method and apparatus is disclosed for preventing loops in a full-duplex bus. One method has the acts of: selecting at least two candidates to join said bus; establishing a dominant candidate from one of said at least two candidates; testing for loops in said bus; ... | 03/20/2007 |
| 7191266 | Method and apparatus for supporting and presenting multiple serial bus nodes using distinct configuration ROM images A method and apparatus for presenting a plurality of link devices as separate nodes within a single serial bus module by generating individual or a distinct configuration ROM image for each link device in the module. Each configuration ROM includes an entry for a di... | 03/13/2007 |
