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| Number | Title | Issue Date |
| 8115527 | PLL apparatus There is provided an art to prevent an unstable operation due to temperature in a PLL apparatus in which a proper range of an amplitude level of an external reference frequency signal is specified and a control voltage is supplied to a voltage-controlled oscillator ... | 02/14/2012 |
| 8115525 | Frequency synthesizer There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output ... | 02/14/2012 |
| 8115526 | PLL oscillator circuit Disclosed is a PLL oscillator circuit capable of examining an unlock state while being equipped with an auto retry function enabling automatic relock. In the PLL oscillator circuit, a MPU receives a lock detection signal from the PLL-IC that receives an external ref... | 02/14/2012 |
| 8111093 | Power supply noise rejection in PLL or DLL circuits A phase controller can be part of a phase-locked loop (PLL) or a delay-locked loop (DLL). The phase controller includes first and second regulators. The first regulator provides power supply noise rejection while the second regulator provides phase and frequency loc... | 02/07/2012 |
| 8111092 | Register with process, supply voltage and temperature variation independent propagation delay path A digital data register is disclosed that provides setup and hold timing on the pre-register side, clock centering on the post-register side, and constant propagation delay time over variations in process, supply voltage and temperature (PVT) using a novel means to ... | 02/07/2012 |
| 8106690 | Semiconductor integrated circuit device To generate a highly accurate SSC while reducing the circuit area of a clock generation circuit that generates a normal clock and an SSC. A clock signal output from a voltage controlled oscillator is frequency-divided by a frequency divider, and is output as a first... | 01/31/2012 |
| 8106691 | Phase adjustment circuit In a phase adjustment circuit that divides the frequency of a double-frequency clock to obtain a 50% duty-cycle clock, a first ½ frequency division circuit having a phase inversion function generates an intermediate reference clock apart in phase from both a phase ... | 01/31/2012 |
| 8102196 | Programmable dual phase-locked loop clock signal generator and conditioner A clock signal generator and conditioner in which dual integrated phase-locked loop (PLL) circuits use an off-chip frequency-pullable crystal resonator or voltage-controlled oscillator (VCO) module and an on-chip VCO with intra-PLL frequency doubling to provide a cl... | 01/24/2012 |
| 8102195 | Digital phase-locked loop circuit including a phase delay quantizer and method of use A phase locked loop circuit in accordance with an embodiment implements a digital phase delay quantizer to replace the analog charge-pump and phase frequency detector in an analog PLL circuit. Therefore, the built-in loop filter can be a compact-sized, high order, h... | 01/24/2012 |
| 8102197 | Digital phase locked loop An adaptive digital phase locked loop comprises: a digital configurable phase detector for receiving a reference signal and a feedback signal and for generating a detection signal indicative of a phase/frequency difference between the reference signal and the feedba... | 01/24/2012 |
| 8085070 | Overclocking with phase selection A novel solution that combines the technologies of fractional divider and phase selection is provided to implement over-clocking for CPU PLL in PC clock generator with a set resolution that is independent of the clock frequency. ... | 12/27/2011 |
| 8076960 | Digital phase-locked loop with two-point modulation using an accumulator and a phase-to-digital converter A digital phase-locked loop (DPLL) supporting two-point modulation is described. In one design, the DPLL includes a phase-to-digital converter and a loop filter operating in a loop, a first processing unit for a lowpass modulation path, and a second processing unit ... | 12/13/2011 |
| 8076961 | Monitoring apparatus and computer-readable storage medium A monitoring apparatus monitors a system including an oscillator with a variable oscillation frequency. The monitoring apparatus has a transmitting unit to transmit an information collecting instruction for collecting state information of the system to the system at... | 12/13/2011 |
| 8067965 | Clock and data recovery circuit with proportional path A clock and data recovery circuit includes a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider. The voltage-controlled oscillator includes a current mirror, a control circuit, a current modulation module and a curr... | 11/29/2011 |
| 8063677 | Phase locked loop and method for operating the same A phase locked loop includes a phase lock unit configured to compare a phase of a reference clock with a phase of a feedback clock and to generate an internal clock based on the comparison; a delay lock unit configured to compare the reference clock with the interna... | 11/22/2011 |
| 8058916 | Lockstep synchronization and maintenance A method and circuit are provided for synchronizing a first circuit and a second circuit. The first and second circuits are signaled to each generate respective waveform outputs. A phase difference is determined between the generated waveform output from the first a... | 11/15/2011 |
| 8058915 | Digital phase-locked loop and digital phase-frequency detector thereof A digital phase-locked loop and a digital phase-frequency detector thereof are provided. The digital PFD includes a divisor switch unit, a low-resolution phase-error detecting unit, an accumulating unit, a high-resolution phase-error detecting unit, a constant unit,... | 11/15/2011 |
| 8058914 | Generating multiple clock phases In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; ... | 11/15/2011 |
| 8054114 | Fractional-N phase-locked loop A fractional-N phase-locked loop (PLL) includes a phase detector, a voltage-controlled oscillator (VCO), a frequency divider and a frequency multiplier with a multiplication factor of a mixed number. The phase detector compares phase difference between a reference f... | 11/08/2011 |
| 8049539 | Circuit with variation correction function A circuit with variation correction function is capable of obtaining an output characteristic near a desired value by suppressing variation of the output characteristic regardless of manufacturing characteristic variations of a component. An output signal different ... | 11/01/2011 |
| 8044692 | Level-restorer for supply-regulated PLL The present disclosure provides for a processor that can include digital processing circuitry that receives a digital clock signal from a supply regulated phase locked loop. The supply regulated phase locked loop can include a voltage controlled oscillator that can ... | 10/25/2011 |
| 8035430 | Signal generator with output frequency greater than the oscillator frequency Systems and methods for design and operation of signal generator circuitry with output frequencies greater than the oscillator frequency. Accordingly, in a first method embodiment, a method of producing an output periodic electronic signal comprises accessing four s... | 10/11/2011 |
| 8022738 | Apparatus and method for detecting the loss of an input clock signal for a phase-locked loop An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and out... | 09/20/2011 |
| 8008955 | Semiconductor device There is provided a semiconductor device having a voltage-controlled oscillator outputting an output clock signal; N pieces of control units generating a frequency-divided clock signal by frequency-dividing the output clock signal, comparing a reference clock signal... | 08/30/2011 |
| 8004322 | Synchronization scheme with adaptive reference frequency correction The present invention relates to an apparatus and method for providing synchronization of an output signal to a synchronization information. The synchronization is accomplished by providing coupling of a correction control information that controls a signal generati... | 08/23/2011 |
| 8004323 | PLL control circuit A PLL control circuit, which outputs a PLL clock in response to a reference clock, is provided with a frequency adjustment circuit which performs frequency adjustment such that the PLL clock frequency is substantially constant even when the reference clock varies. T... | 08/23/2011 |
| 8004327 | Phase locked oscillator and radar unit having the same An error detecting unit of a phase-locked oscillator evaluates difference between a reference phase error signal output from a phase detector and a phase error signal actually output from the phase detector when a reference frequency modulation signal is output from... | 08/23/2011 |
| 8004325 | Semiconductor device having controlled DLL start-up period A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from th... | 08/23/2011 |
| 8004326 | Digital charge pump PLL architecture A digital phase lock loop (PLL) circuit having a digital charge pump circuit for providing digital signals corresponding to a difference in phase between an internal clock corresponding to a voltage controlled oscillator, and a reference clock. These digital signals... | 08/23/2011 |
| 8004324 | Phase-locked loop frequency synthesizer of fractional N-type, and phase shift circuit with frequency converting function Provided is a phase-locked loop frequency synthesizer, including: a reference oscillator; a voltage controlled oscillator; a variable frequency divider that divides the high frequency signal in frequency to output a feedback signal; a phase comparator that compares ... | 08/23/2011 |
| 7999584 | Method and apparatus for on-chip phase error measurement to determine jitter in phase-locked loops An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error sign... | 08/16/2011 |
| 7999583 | Method and apparatus for on-chip phase error measurement to determine jitter in phase-locked loops An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error sign... | 08/16/2011 |
| 7994829 | Fast lock-in all-digital phase-locked loop with extended tracking range An apparatus and a method for achieving lock-in of a phase-locked loop (PLL) are disclosed. The PLL receives a reference clock and generates an output clock according to the reference clock. The method comprises: adjusting an oscillation frequency of a controlled os... | 08/09/2011 |
| 7990191 | Digital phase-locked loop A digital phase-locked loop circuit includes: a first counter which counts a first clock; a second counter which counts third clocks into which a second clock is divided; a first phase detector which detects a relative phase difference between the first and the thir... | 08/02/2011 |
| 7986176 | Clock generating apparatus and clock generating method A clock generating apparatus includes a phase-difference measuring device for measuring a difference in phase between a reference clock and a feedback clock generated by a divider with a high-speed clock generated by a multiplier, an averager for averaging the measu... | 07/26/2011 |
| 7973576 | Voltage controlled oscillators and phase-frequency locked loop circuit using the same A voltage controlled oscillator comprising first and second differential delay cells. The first differential delay cell has a first control voltage input terminal. The second differential delay cell is coupled to the first differential delay cell in a loop and has a... | 07/05/2011 |
| 7965582 | Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving r... | 06/21/2011 |
| 7952403 | Update control apparatus in DLL circuit An update control apparatus in a DLL circuit is provided. The update control apparatus includes a logic value determination, a phase information collection unit, and an update control unit. The logic value determination unit is configured to determine a logic value ... | 05/31/2011 |
| 7948285 | PLL circuit, radio terminal device and control method of PLL circuit There is provided a PLL circuit including a phase comparison unit that compares an accumulated addition value of a division ratio converted into a digital value and that of an oscillating signal from an oscillator controlled by using the digital value in each cycle ... | 05/24/2011 |
| 7944256 | Semiconductor integrated circuit device High precision of various feedback systems represented by a PLL circuit and the like is realized. For example, in a charge pump circuit in the PLL circuit, a first to a third PMOS transistors connected in series in three stages are provided between a power source vo... | 05/17/2011 |
