Class 327/154 - With feedforward

Subclass of Class 327 - Miscellaneous active electrical nonlinear devices, circuits, and systems
Definition: Subject matter wherein a portion of an input signal is advanced
No. of patents: 84
Last issue date: 04/10/2012

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Number	Title	Issue Date
8154327	Phase adjusting apparatus and camera A phase adjusting apparatus includes a comparison code generating section, a calculating section, and a delay section. The comparison code generating section individually generates a first comparison code having a phase of a head code advanced and a second compariso...	04/10/2012
7958469	Design structure for a phase locked loop with stabilized dynamic response A design structure for a hybrid phase locked loop (PLL) circuit that obtains stabilized dynamic response and independent adjustment of damping factor and loop bandwidth is provided. The hybrid PLL circuit of the illustrative embodiments includes the resistance/capac...	06/07/2011
7356551	Method and apparatus of retaining maximum speed of flip-flop metastability based random number generators An apparatus, system and method for retaining the maximum speed of flip-flop metastability based random number generators includes a fixed delay unit having an input for receiving a common signal from a digital signal generator, and a variable delay unit having an i...	04/08/2008
7327181	Multiple phase simultaneous switching preventing circuit, PWM inverter and its driving method A PWM inverter in which high-surge voltage is not applied across terminals of a switching device thereof is provided by preventing multi-phase simultaneous switching. A multi-phase simultaneous-switching prevention circuit (100) that includes: a plurality of ...	02/05/2008
7319728	Delay locked loop with frequency control A delay locked loop includes a delay line for delaying an input signal generated from an external signal. A delay controller controls the delay line to keep the external and internal signals synchronized. The delay locked loop also includes cycle control circuitry f...	01/15/2008
7279944	Clock signal generator with self-calibrating mode A clock signal generator and method thereof are provided for a system to generate an output signal. The apparatus comprises: a delay circuit for generating a delayed clock with a first time, a delay module for generating delayed signal(s), and a decision circuit for...	10/09/2007
7256566	Method and apparatus for determining a maximum power point of photovoltaic cells The maximum power point (MPP) of a photovoltaic array that can be coupled to power inverter is determined. A capacitor on a DC-bus side of the inverter is used as a load from which I-V characteristics of the photovoltaic array can be generated. The photovoltaic arra...	08/14/2007
7230495	Phase-locked loop circuits with reduced lock time PLL circuits are provided in which a voltage-controlled oscillator (VCO) comprising one or more voltage-controlled delay units (VCDs) is initialized with the control voltage of a voltage-controlled delay line (VCDL) having substantially identical VCDs. In general, V...	06/12/2007
7219316	Multi-valued or single strength signal detection in a hardware description language A method, module, and program product for detecting signal strengths in a hardware description language, such as Verilog, that does not provide for such detection. The method includes the steps of creating a wired net configuration that provides for a data input sig...	05/15/2007
7205937	Non-multiple delay element values for phase shifting Non-multiple delay element values that may be implemented to reduce periodic quantization errors associated with phase shifting devices used in phased array apparatus. The non-multiple delay element values may be implemented so that a magnitude of phase shift impart...	04/17/2007
7194671	Mechanism handling race conditions in FRC-enabled processors An processor includes first and second execution cores that operate in an FRC mode, an FRC check unit to compare results from the first and second execution cores, and an error check unit to detect recoverable errors in the first and second cores. The FRC check unit...	03/20/2007
7161399	System and method to improve the efficiency of synchronous mirror delays and delay locked loops A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore increase the efficiency, is disclosed. The invention includes taking a clock input signal and a clock delay ...	01/09/2007
7162000	Delay locked loop synthesizer with multiple outputs and digital modulation A delay locked loop circuit (200) in which multiple outputs are produced. A single delay line (24) is shared among multiple tap selection circuits (256A, 265B, 265C). Fixed phase shifts (412) can be introduced between multip...	01/09/2007
7151519	Liquid crystal display A liquid crystal display includes: a plurality of pixels: a data driver including a memory and a register and supplying data signals to the pixels; and a signal controller supplying a control signal for controlling the data driver to the data driver, wherein the reg...	12/19/2006
7123542	Memory having internal column counter for compression test mode A memory circuit comprises a memory and an internal column counter for a read sequence in a compression test mode of the memory. The memory comprises an array of memory cells. The internal column counter is configured to provide a first column address for generating...	10/17/2006
7110423	Method and system for source synchronous clocking A source synchronous clocking synchronizes data and clock signals transmitted between an ATM layer and a link layer. The source synchronous clocking includes a source clock domain in a first layer which includes a register having a first input for receiving a data s...	09/19/2006
7069359	Circuit and technique to stall the communication of data over a double pumped bus An apparatus includes a first circuit and a second circuit. The first circuit receives indications of first data that is associated with a first data set and second data that is associated with a second data set. The second circuit is coupled to the first circuit to...	06/27/2006
6989696	System and method for synchronizing divide-by counters A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 1...	01/24/2006
6971052	Semiconductor integrated circuit and method for testing the same When a test command is received n times, any one of a plurality of tests is started. After the first test is started, any one of the tests is started or terminated every time the test command is received a predetermined number of times which is less than the n times...	11/29/2005
6965272	Worldwide marketing logistics network including strategically located centers for frequency programming crystal oscillators to customer specification A worldwide logistics network includes a processing center for receiving customer orders for crystal oscillators over communications links, processing the orders, and generating work orders that are selectively disseminated over communications links to programming c...	11/15/2005
6954113	Programmable oscillator circuit A programmable crystal oscillator is provided having a memory for storing frequency-defining parameters. Typically, one of these parameters is used to program an adjustable capacitive load circuit coupled to a crystal to thereby adjust the crystal source frequency. ...	10/11/2005
6944252	Phase comparator circuit A data signal DATA is captured by flip-flops 10 and 11 alternately every half cycle time of a clock signal CLK, outputs of the flip-flops 10 and 11 are delayed by respective delay circuits 15 and 16 to generate delayed signa...	09/13/2005
6930522	Method and apparatus to delay signal latching A first circuit is to generate a data signal containing data. A second circuit is to utilize said data, where the first and second circuits are commonly clocked by a latch signal, further a circuit has a first level sensitive latch to latch the data signal from the ...	08/16/2005
6930979	Method and system for multi-PHY addressing Multi-PHY addressing from source to destination in which n-number of channels or ports are used in a PHY layer device for communication with a link layer device. A single link layer to a single-PHY layer topology and a single link layer to a multi-PHY layer topology...	08/16/2005
6922359	Nonvolatile semiconductor memory device allowing high speed data transfer Local buses for performing writing/reading of data are provided in correspondence to memory blocks each having a plurality of nonvolatile memory cells, and also circuits for performing writing/reading of data are provided in correspondence to the memory blocks. In a...	07/26/2005
6891412	Low noise filter An RC equivalent filter is provided in which the resistor is replaced by a voltage source (40) and a capacative divider. With suitable control the voltage occurring across a capacitor (44) in the divider can reproduce that which would occur across at t...	05/10/2005
6861882	Semiconductor integrated circuit with reduced leakage current A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores a...	03/01/2005
6839092	Feed forward error correction in video decoder In accordance with an embodiment of the present invention a microprocessor in the horizontal phased lock loop reads the horizontal timing with respect to the sync input and provides an increment inch to the horizontal discrete time oscillator to make corr...	01/04/2005
6839301	Method and apparatus for improving stability and lock time for synchronous circuits Delay-locked loops, signal locking methods and devices and system incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase detector and a timer circuit. The forward delay path alternatively cou...	01/04/2005
6792060	Processor having an adaptable operational frequency The invention relates to a processing device for digital data which is capable of processing data which have been sampled with a sampling clock which may have any value whatsoever with respect to the basic clock of the device. To achieve this, the device is provided...	09/14/2004
6782353	Instrument for measuring characteristic of data transmission system with high accuracy and clock reproducing circuit used therefor The present invention provides a measuring device which extracts, from an inputted data signal, a clock signal in which there is little internal occurrence of absence or phase fluctuations, and correctly carries out measurement of an error ratio or jitter or wander ...	08/24/2004
6781426	Nanosecond monolithic CMOS readout cell A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the...	08/24/2004
6762630	Integrated circuit having a synchronous and an asynchronous circuit and method for operating such an integrated circuit An integrated circuit has a synchronous circuit and an asynchronous circuit. A clock-controlled input register circuit and an output register circuit for storing data are each connected to the synchronous circuit and the asynchronous circuit. Data are transferred fr...	07/13/2004
RE38482	Delay stage circuitry for a ring oscillator A ring oscillator includes an even-numbered plurality of ring coupled delay stages. Each delay stage includes a differential amplifier, a voltage clamping circuit, and a current source. The differential amplifier receives first and second input signals from a preced...	03/30/2004
6654296	Devices, circuits and methods for dual voltage generation using single charge pump Devices, circuits and methods for dual voltage generation using a single charge pump. The dual voltages can be the same or different, as they are for two different components of a device. An oscillator generates an oscillating signal, and a charge pump ge...	11/25/2003
6639438	Apparatus and method for communication link having parallel signal detect with hysteresis A method is described that involves directing a signal through a hysteresis comparator. Then, determining if an output signal of the hysteresis comparator, in response to the signal, is an AC signal or a DC signal. Then, deactivating a signal reception un...	10/28/2003
6529054	Prefetch architectures for data and time signals in an integrated circuit and methods therefor A synchronized data capture circuit configured to synchronize capturing of data in a first plurality of data signals with a first plurality of timing signals to output a synchronized data capture signal. The synchronized data capture circuit includes a ti...	03/04/2003
6415008	Digital signal multiplier An electronic circuit that multiplies an input signal using primarily digital components so that the resulting circuit can be fabricated consistently by different foundries. The circuit determines a period for the input signal and converts the period to a...	07/02/2002
6356126	Methods and devices for testing the operation of counters used in phase-locked loops Intermittent miscounts generated by counters used in a phase-locked loop ("PLL") are precisely measured by detecting changes to a predetermined waveform, such as a sawtooth waveform. The miscounts are detected using an open loop, not closed loop, set-up w...	03/12/2002
6242956	Phase locked loop A hybrid phase locked loop employs both analog and digital circuitry. A digital to analog converter (DAC) provides a current output signal in conjunction with a current controlled oscillator (ICO). The hybrid phase locked loop employs the digital circuitr...	06/05/2001

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Class 327/154 - With feedforward