Famous Patents
Felix Hoffmann, a German chemist, was searching for something to relieve his father's arthritis. In doing so, he "rediscovered" acetylsalicylic acid and in 1900, patented a stable process for developing it. Hence, we have aspirin.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7436919 | Methods and apparatus for bit synchronizing data transferred across a multi-pin asynchronous serial interface Methods, devices and systems are provided for bit synchronizing multiple serial bitstreams (106) with a common clock signal (116). Activity occurring in each bitstream is detected (304) for each of a plurality of phases corresponding to cycles o... | 10/14/2008 |
| 7398412 | Measure controlled delay with duty cycle control The disclosed embodiments relate to circuits that produce synchronized output signals. More specifically, there is provided a synchronization circuit adapted to receive an input signal, the synchronization circuit comprising a delay monitor adapted to produce a dela... | 07/08/2008 |
| 7397882 | Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase compar... | 07/08/2008 |
| 7368939 | Data input/output circuit included in semiconductor memory device A control circuit receives an external control signal in synchronism with an internal clock and generates an address signal and internal control signals. A data multiplexer has a plurality of input parallel lines and a plurality of output parallel lines and is switc... | 05/06/2008 |
| 7345933 | Qualified data strobe signal for double data rate memory controller module A circuit generates a qualified data read strobe signal from a start burst signal and a bidirectional data strobe signal in a DDR memory control module. The circuit includes a delay module that receives the start burst signal and that generates a delayed start burst... | 03/18/2008 |
| 7317775 | Switched deskew on arbitrary data A method and circuit capable of handling skew between a clock and data signal up to +/− one half bit on a random input data pattern. A digital algorithm cycles through each data bit and individually deskews that bit by detecting data transitions in a first samplin... | 01/08/2008 |
| 7256627 | Alignment of local transmit clock to synchronous data transfer clock having programmable transfer rate A phase alignment circuit having a phase selection circuit, a synchronizer, and a counter form a feedback loop for aligning a local clock signal with a received reference clock of a synchronous communications system. The phase selection circuit is configured for out... | 08/14/2007 |
| 7225349 | Power supply voltage droop compensated clock modulation for microprocessors A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected. ... | 05/29/2007 |
| 7212049 | Digital-control-type phase-composing circuit system A digital-control phase-composing circuit system has a phase-composing circuit which is supplied with two input clock signals having a phase difference therebetween and a control signal, and which composes an output clock signal having a phase between the phases of ... | 05/01/2007 |
| 7194056 | Determining phase relationships using digital phase values Disclosed herein are circuits in which a plurality of clock signals are generated by corresponding clock generators from one or more common clock references. The clock generators accept control values that specify the phases of the individual clocks. The actual phas... | 03/20/2007 |
| 7167031 | Synchronizing circuit provided with hysteresis phase comparator A synchronizing circuit includes a phase comparator having hysteresis characteristics and a dead zone, and configured to generate a frequency division ratio control signal based on a phase difference between a first clock and a second clock. The circuit further incl... | 01/23/2007 |
| 7157948 | Method and apparatus for calibrating a delay line A delay line calibration circuit and method are provided in which a programmable master delay line drives a delay clock and has a propagation delay that is a function of a delay setting. A delay counter is clocked by the delay clock and has a delay count. A referenc... | 01/02/2007 |
| 7154305 | Periodic electrical signal frequency monitoring systems and methods Systems and methods for monitoring frequencies of periodic electrical signals are disclosed. According to one technique, a first and second counters are respectively clocked by a first periodic electrical signal to be monitored and a second periodic electrical, and ... | 12/26/2006 |
| 7095254 | Method for producing a control signal which indicates a frequency error A method which provides a very simple way of forming a control signal if the frequencies differ too greatly from one another between a useful signal and a reference signal. A control signal is produced which indicates that the frequency error between the frequencies... | 08/22/2006 |
| 7095353 | Frequency to digital conversion A technique of processing an input signal having an input signal phase is disclosed. The technique includes determining a number of transitions of the input signal within a period having a start and an end. The technique includes determining a relative beginning pha... | 08/22/2006 |
| 7092478 | Local timer which is used in wireless LAN A local timer includes a dividing counter which counts a first clock and outputs a reference counting signal divided from the first clock; a timing synchronizing timer which counts a timing synchronizing timer value in synchronization with a reference timer responsi... | 08/15/2006 |
| 7076014 | Precise synchronization of distributed systems A method for synchronizing a plurality of sub-systems, comprising the steps of measuring a relationship between a divider associated with each of the plurality of sub-systems; and adjusting a phase of one or more of the dividers to a known relationship with one of t... | 07/11/2006 |
| 7065169 | Detection of added or missing forwarding data clock signals A system is disclosed that detects data forwarding clock errors including both missing and additional clock signals. The system provides for a phase locked loop (PLL) that locks onto a data forwarding source synchronous clock signal wherein the PLL outputs a system ... | 06/20/2006 |
| 7047434 | Data transfer control device and electronic equipment The objective is to provide a data transfer control device and electronic equipment that make it possible to switch the frequency of a generated clock dynamically, without causing any operating errors. The data transfer control device includes a clock generation cir... | 05/16/2006 |
| 7005899 | Frequency division/multiplication with jitter minimization A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the inventio... | 02/28/2006 |
| 6959064 | Clock recovery PLL A multimode clock recovery circuit for providing constant bit rate services in a cell relay network has an embedded digital phase locked loop including an input circuit capable of generating a phase signal from at least two types of input signal. The phase signal co... | 10/25/2005 |
| 6952121 | Prescaling for dividing fast pulsed signal Circuits, devices and methods are provided for dividing a fast pulse signal by an integer M. A dual modulus prescaler receives input pulses, counts them, and generates one prescaled pulse for every Qth input pulse. Q is a division modulus, and has a different value ... | 10/04/2005 |
| 6930519 | Frequency division/multiplication with jitter minimization A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the inventio... | 08/16/2005 |
| 6925139 | Microprocessor comprising a self-calibrated time base circuit The present invention relates to an integrated circuit comprising a first clock circuit delivering a first clock signal, a second clock circuit delivering a second clock signal, a first counting circuit for delivering a time base signal using a clock signal and a co... | 08/02/2005 |
| 6922084 | Ultra-low power programmable timer and low voltage detection circuits An Ultra-low power voltage detection circuit is implemented in a digital integrated circuit to device to provide a basic timer, programmable timer and programmable low voltage detection (PLVD) using a single connection of the digital integrated circuit device and a ... | 07/26/2005 |
| 6909762 | Phase-locked loop circuit Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device for monitoring the frequency discrepancy between two signals in conjunction with at least one data signal s... | 06/21/2005 |
| 6904539 | Method of determining data transfer speed in data transfer apparatus A method of determining a transfer speed of an encoded data signal including a clock signal and a data signal is provided. First, the encoded data signal is decoded to generate a decoded clock signal. Then, a data transfer speed of the encoded data signal is determi... | 06/07/2005 |
| 6873215 | Power down system and method for integrated circuits A power down system and method for an integrated circuit that enables a power down mode to be maintained for a predetermined time is described herein. The power down system comprises an oscillator, a low power oscillator and an oscillator control circuit controlling... | 03/29/2005 |
| 6862332 | Clock reproduction circuit A master clock signal source (10) generates a master clock signal having a frequency equal to N times the bit rate of received data, where N is a positive integer. A modulo-N counter (12) counts the master clock signal. An edge detecting circuit (4 | 03/01/2005 |
| 6859109 | Double-data rate phase-locked-loop with phase aligners to reduce clock skew A phase-locked loop (PLL) has an analog divider in the feedback path that receives either the in-phase or quadrature-phase pair of outputs from a voltage-controlled oscillator (VCO) while the other pair, 90-degree out-of-phase, of outputs from the VCO is used for th... | 02/22/2005 |
| 6731144 | Delay lock loop circuit, variable delay circuit, and recording signal compensating circuit The present invention is intended to provide a delay lock loop circuit which is capable of providing a minute delay amount with stability regardless of the variations in delay amount due to variations in temperature and power supply voltage for example and process c... | 05/04/2004 |
| 6721377 | Method and circuit configuration for resynchronizing a clock signal A method for resynchronizing a clock signal, includes the steps of defining a presettable clock signal, dividing a first clock signal having a first frequency with a programmable digital frequency divider to produce a second clock signal having a second frequency, m... | 04/13/2004 |
| 6714056 | Frequency division/multiplication with jitter minimization A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a PhaseLock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the in... | 03/30/2004 |
| 6701445 | Frequency control system that stabilizes an output through both a counter and voltage-controlled oscillator via sampling a generated clock into four states A frequency control system includes a voltage-controlled oscillator, a sampling circuit for sampling a clock signal produced by the oscillator for two consecutive transitions of an unstable incoming digital signal, and a frequency comparator for increment... | 03/02/2004 |
| 6657463 | System for maintaining the stability of a programmable frequency multiplier A programmable frequency multiplier receives data representing a desired multiplication ratio from a first configuration register. The ratio data is transferred to the frequency multiplier concurrently with the generation of an internal delayed reset sign... | 12/02/2003 |
| 6639958 | Circuit configuration for the interference-free initialization of delay locked loop circuits with fast lock The invention relates to a circuit configuration for the interference-free initialization of delay locked loop circuits with fast lock. A control signal for rapidly adjusting the DLL circuit is converted into a delayed control signal, which is kept consta... | 10/28/2003 |
| 6597753 | Delay clock generating apparatus and delay time measuring apparatus A standard clock 34 is input to a phase comparator 52 and a phase controller 56. The ring oscillator 50 oscillates a shift clock 70 having a same cycle as the standard clock 34. The phase comparator 52 matches the downward shift of the shift clock 70 with... | 07/22/2003 |
| 6594330 | Phase-locked loop with digitally controlled, frequency-multiplying oscillator A phase-locked loop (PLL) having a digitally controlled oscillator (DCO), where the DCO receives a digital control signal generated by the PLL and an externally generated oscillator clock signal and generates an output signal having a frequency greater th... | 07/15/2003 |
| 6591370 | Multinode computer system with distributed clock synchronization system A multinode multiprocessor computer system with distributed local clocks wherein a local clock may be synchronized with other clocks in the system without affecting the operation of the other clocks. A local clock to be synchronized is reset and counts an... | 07/08/2003 |
| 6583655 | Clock control circuit A clock control circuit includes a ring counter for outputting a signal of N bits count value and a complementary signal thereof; a rescue & flag generating circuit for effecting rescue from a bit pattern that is outside of expectations and generating a f... | 06/24/2003 |
