Did You Know...
...that in the early 1940s GE engineer James Wright was charged with a task of utmost importance to the war effort: develop a cheap substitute for rubber that could be used to produce tires, gas masks and a whole host of military gear. Wright tackled the task diligently -- and wound up inventing Silly Putty.
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| Number | Title | Issue Date |
| 8179173 | Digitally calibrated high speed clock distribution An electronic circuit for distributing a clock signal to several clock destinations includes phase adjustment circuits for adjusting phase shifts of the clock at the respective one of the clock destinations responsive to a respective DC voltage feedback signal recei... | 05/15/2012 |
| 7443743 | Method and system for improved efficiency of synchronous mirror delays and delay locked loops A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multipl... | 10/28/2008 |
| 7423919 | Method and system for improved efficiency of synchronous mirror delays and delay locked loops A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multipl... | 09/09/2008 |
| 7372299 | Differential clock tree in an integrated circuit A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a ... | 05/13/2008 |
| 7327173 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 02/05/2008 |
| 7288975 | Method and apparatus for fail-safe and restartable system clock generation A method and apparatus for fail-safe and restartable system clock generation provides recovery from failures due to incorrect clock generator settings or from marginal clock distribution components. Clock failure is detected at a point along the clock distribution p... | 10/30/2007 |
| 7277133 | Adjusting pixel clock A pixel clock frequency is adjusted in response to periodically monitoring the relative positions between a video signal to be displayed and a video signal captured. Image shear of the display signal may be avoided quickly. Adjustments are made to the color burst si... | 10/02/2007 |
| 7271545 | Ballast and igniter for a lamp having larger storage capacitor than charge pump capacitor A ballast according to the present invention operates in an ignition state, a warm-up state, and a steady state for igniting and powering a lamp. The ballast comprises an igniter that ignites the lamp during the ignition state and a switching power inverter, for exa... | 09/18/2007 |
| 7256627 | Alignment of local transmit clock to synchronous data transfer clock having programmable transfer rate A phase alignment circuit having a phase selection circuit, a synchronizer, and a counter form a feedback loop for aligning a local clock signal with a received reference clock of a synchronous communications system. The phase selection circuit is configured for out... | 08/14/2007 |
| 7239575 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 07/03/2007 |
| 7200451 | Method for consistent on/off object to control radios and other interfaces In a method and system for controlling a device coupled to an information handling system, an object is defined to include a hardware and software component having a corresponding hardware operating state and a software operating state. The hardware component is ope... | 04/03/2007 |
| 7196564 | High frequency balanced phase interpolator A phase interpolation system includes an input stage that provides first and second modulated input signals having selected first and second relative phase angles. A weighting system is configured to steer a first portion of the first modulated input signal to an ou... | 03/27/2007 |
| 7129765 | Differential clock tree in an integrated circuit A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a ... | 10/31/2006 |
| 7120217 | Phase-locked loop circuit In a PLL circuit including a voltage-controlled oscillator, a phase detector and a final control element, the final control element contains two separate channels, between the phase detector and the voltage controlled oscillator, wherein one channel processes the us... | 10/10/2006 |
| 7106111 | Clock adjustment Circuits and methods are provided for clock adjustment. A method for clock adjustment includes receiving feedback clocks from independent ASIC modules. The method includes comparing the feedback clocks to a reference clock to generate phase measurement values. A com... | 09/12/2006 |
| 7092478 | Local timer which is used in wireless LAN A local timer includes a dividing counter which counts a first clock and outputs a reference counting signal divided from the first clock; a timing synchronizing timer which counts a timing synchronizing timer value in synchronization with a reference timer responsi... | 08/15/2006 |
| 7088156 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 08/08/2006 |
| 7084678 | Fractional frequency divider A frequency divider device includes a divider input and a phase count and select section. The phase count and select section includes at least two phase count and select inputs each communicatively connected to the divider input (for receiving each at least one phas... | 08/01/2006 |
| 7062733 | Method and apparatus for delay line calibration Sub-sampled signals are compared to determine time delay, calibration of delay elements, and other precise time domain measurements, based on properties of aliased signals produced by the sub-sampling. In one embodiment, flip-flops sub-sample an input signal and a d... | 06/13/2006 |
| 7049868 | System and method for compensating for supply voltage induced clock delay mismatches Various systems and methods providing signal delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog implementation a buffer with an adjustable delay may be used to minimize the delay mismatch between clock trees... | 05/23/2006 |
| 7035366 | Delay locked loop circuit and its control method A delay locked loop (DLL) circuit comprising: a fundamental phase comparator for detecting a fundamental phase difference of two input signals; a delay circuit; a delay control circuit for adjusting a delay time of the delay circuit in response to an output signal o... | 04/25/2006 |
| 7016259 | Apparatus for calibrating the relative phase of two reception signals of a memory chip A calibration apparatus is provided for adjusting the relative phase between two signals received at a memory chip, the two signals being generated such that they are synchronized with one another in a controller and are transmitted to the memory chip via separate l... | 03/21/2006 |
| 7012985 | Frequency division of an oscillating signal involving a divisor fraction A frequency-divider circuit performs a division operation using a divisor that can include a fraction. In one such embodiment, a first divider module includes a divider circuit that operates to divide the frequency of an input clock signal and a phase-quadrature cir... | 03/14/2006 |
| 6973155 | Highly scalable glitch-free frequency divider The present invention provides for a divider circuit for reducing anomalous output timing pulses. A latch is coupled to the division selection line. A comparator is coupled to the division selection line. A first synchronizer coupled to the output of the latch. A fr... | 12/06/2005 |
| 6969984 | Direct phase and frequency demodulation The present invention, generally speaking, provides a time shift angle demodulator that is of simple construction and has an extended linear range. Range extension is achieved by using the input signals directly, not simply post-processing the S-PFD outputs. In acco... | 11/29/2005 |
| 6963628 | Multiphase retiming mechanism A system and method for reducing timing uncertainties in a serial data signal. A system may comprise a transmitter configured to transmit serial data to a receiver through a transmission medium. The receiver may comprise a retiming mechanism configured to sample the... | 11/08/2005 |
| 6954091 | Programmable phase-locked loop An integrated circuit is provided, which includes a phase-locked loop (PLL) that is fabricated on the integrated circuit and has a selectable loop filter capacitance and a selectable output frequency range. ... | 10/11/2005 |
| 6943844 | Adjusting pixel clock A pixel clock frequency is adjusted in response to periodically monitoring the relative positions between a video signal to be displayed and a video signal captured. Image shear of the display signal may be avoided quickly. Adjustments are made to the color burst si... | 09/13/2005 |
| 6940352 | Analog signal interpolation A linear interpolator is provided that includes differential pairs of transistors biased such that a first input voltage may be multiplied by a factor r wherein 0≦r≦1 and such that a second input voltage may be multiplied by the complement factor (1−r). By com... | 09/06/2005 |
| 6937948 | Flash memory program and erase operations A flash memory device includes a charge pump having a capacity that is preset to a particular value. The flash memory device includes a measuring circuit to measure the actual capacity of the charge pump and to reset the capacity of the charge pump to a value based ... | 08/30/2005 |
| 6924675 | Buffer device A buffer device includes a plurality of latch stages which each have a latch device and a multiplexer. At least the multiplexer of the first latch stage on the output side is associated with a feedback loop of the latch device of this latch stage. The feedback loop ... | 08/02/2005 |
| 6925139 | Microprocessor comprising a self-calibrated time base circuit The present invention relates to an integrated circuit comprising a first clock circuit delivering a first clock signal, a second clock circuit delivering a second clock signal, a first counting circuit for delivering a time base signal using a clock signal and a co... | 08/02/2005 |
| 6888580 | Integrated single and dual television tuner having improved fine tuning Improved television tuning circuits are disclosed. An example tuning circuit includes a fraction-N frequency synthesizer facilitating fine tuning. This tuning circuit may be formed using relatively few independent oscillators. The tuning circuit lends itself to the ... | 05/03/2005 |
| 6856658 | Digital PLL circuit operable in short burst interval A digital PLL (phase locked loop) circuit includes a sampling circuit, a plurality of internal circuits and an output switching circuit. The sampling circuit samples a burst data signal in response to a multi-phase clock signal to produce N (N is a positive integer ... | 02/15/2005 |
| 6842055 | Clock adjustment Circuits and methods are provided for clock adjustment. A method for clock adjustment includes receiving feedback clocks from independent ASIC modules. The method includes comparing the feedback clocks to a reference clock to generate phase measurement values. A com... | 01/11/2005 |
| 6826248 | Phase locked loop circuit There is disclosed a phase locked loop circuit comprising a phase frequency comparator configured to output an up/down signal indicating a phase difference and a frequency difference between a reference signal and a frequency divided signal, a charge pump configured... | 11/30/2004 |
| 6823029 | System for managing signals in different clock domains and a programmable digital filter A synchronizer circuit manages signals in different clock domains by generating clock pulses synchronized with a system clock. The clock pulses are generated at a rate proportional to the frequency of a clock operating in a first clock domain. Digital circuitry is t... | 11/23/2004 |
| 6753740 | Method and apparatus for calibration of a post-fabrication bias voltage tuning feature for self biasing phase locked loop A calibration and adjustment system for post-fabrication control of a phase locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is cont... | 06/22/2004 |
| 6737896 | Synchronous circuit A synchronous circuit according to an embodiment of the present invention, comprising: a clock selector configured to select a suitable phase clock signal from a plurality of clock signals differing in phase from each other in accordance with a clock-selectin... | 05/18/2004 |
| 6657463 | System for maintaining the stability of a programmable frequency multiplier A programmable frequency multiplier receives data representing a desired multiplication ratio from a first configuration register. The ratio data is transferred to the frequency multiplier concurrently with the generation of an internal delayed reset sign... | 12/02/2003 |
