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| Number | Title | Issue Date |
| 7576569 | Circuit for dynamic circuit timing synthesis and monitoring of critical paths and environmental conditions of an integrated circuit A circuit for dynamically monitoring the operation of an integrated circuit under differing temperature, frequency, and voltage (including localized noise and droop), and for detecting early life wear-out mechanisms (e.g., NBTI, hot electrons). ... | 08/18/2009 |
| 7320049 | Detection circuit for mixed asynchronous and synchronous memory operation A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode ... | 01/15/2008 |
| 7279873 | Current-limited protection circuit of switching power converter A switching power converter comprises a switch, a pulse width modulation (PWM) circuit, a rectifying filter circuit and a current limited protection circuit. The input terminal of the rectifying filter circuit is coupled to an input voltage via the switch. The curre... | 10/09/2007 |
| 7219294 | Early CRC delivery for partial frame Memory apparatus and methods transmit and receive a CRC code for a first portion of a frame before the second portion of the frame is finished being transferred. The CRC may be used to check the first portion of the frame before the second portion of the frame is co... | 05/15/2007 |
| 7205797 | Common mode detection and dynamic correction input circuit A single ended input circuit can receive an input signal and generate a correction voltage corresponding to a common mode voltage of the input signal. A comparison of the input signal can be adjusted in response to the correction voltage. In one arrangement, an inpu... | 04/17/2007 |
| 7203779 | Fast turn-off slow turn-on arbitrator for reducing tri-state driver power dissipation on a shared bus A bus arbitrator for use in a shared bus system in which N bus devices request access to a shared bus. The bus arbitrator slowly activates and rapidly de-activates tristate line drivers coupled to the shared bus. The bus arbitrator comprises: 1) an input interface f... | 04/10/2007 |
| 7190192 | High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high freq... | 03/13/2007 |
| 7126383 | High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high freq... | 10/24/2006 |
| 7120555 | Signal statistics determination A signal can be analysed to determine statistical characteristics indicative of, for example, the predictability or time reversibility of the signal. The signal is examined to locate events corresponding to the crossing of predetermined levels with predetermined slo... | 10/10/2006 |
| 7106637 | Asynchronous interface circuit and method for a pseudo-static memory device An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address inte... | 09/12/2006 |
| 7098696 | Logic circuit and semiconductor integrated circuit The invention provides a logic circuit to identify time difference between signals having a variation in delay, and an integrated circuit which can evaluate variations in delay among internal signals. By using a logic circuit which outputs different number of pulse ... | 08/29/2006 |
| 7054250 | Method and device for jitter enhancement in an optical disc system A method and device are provided for jitter enhancement in an optical disc system. The optical disc system generates a signal that includes an effective component having a first slew rate, and a pre-pit component having a second slew rate larger than the first slew ... | 05/30/2006 |
| 7009428 | High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high freq... | 03/07/2006 |
| 7006159 | Adapter circuit for audio and video signals A circuit arrangement includes at least one adapter circuit (10). which amplifies an analog input signal of a low current (Ii) by an amplification factor (n) into a particularly analog output signal of a higher current (Io). The adapter ... | 02/28/2006 |
| 6998879 | Level determination circuit determining logic level of input signal An input circuit in a DRAM includes a differential amplifier circuit amplifying a potential difference between a potential of an input signal and a reference potential, an inverter outputting an inversion signal of an output signal of the differential amplifier circ... | 02/14/2006 |
| 6975559 | Device and method for reading non-volatile memories having at least one pseudo-parallel communication interface The invention relates to a method for testing non-volatile memory devices that have at least one parallel communication interface, and a conventional matrix of non-volatile memory cells with respective reading, changing and erasing circuits, wherein during the testi... | 12/13/2005 |
| 6650149 | Latched active fail-safe circuit for protecting a differential receiver A fail-safe circuit for a differential receiver can tolerate noise. A latch is enabled when both differential inputs V+, V- rise above a reference voltage that is close to Vcc. The latch, once enabled, is set by an offset amplifier, signaling the fail-saf... | 11/18/2003 |
| 6255859 | High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit fo... | 07/03/2001 |
| 6225832 | Signal regeneration circuit The signal regeneration circuit recovers a digital signal from an input signal that is supplied via metallic isolation (galvanic separation). The circuit has two input terminals for the input signal and one output terminal for the recovered digital signal... | 05/01/2001 |
| 6209051 | Method for switching between multiple system hosts In a method for switching between multiple system hosts (154,164,174,184) on a CompactPCI bus (110,120), a hot swap controller (166,186) provides to a special arbiter (820) a high priority request signal and the special arbiter (820) provides to the hot s... | 03/27/2001 |
| 6201417 | Shaping a current sense signal by using a controlled slew rate A method and circuit for reducing the leading edge spike in a current sense signal. The current sense signal is a measure of the current through a switched power device controlled by a switching regulator controller. The slew rate of the current sense sig... | 03/13/2001 |
| 6160423 | High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit fo... | 12/12/2000 |
| 6100680 | Detecting the passing of magnetic articles using a transducer-signal detector having a switchable dual-mode threshold A magnetic-field-to-voltage transducer includes a Hall element and a digitally gain-controlled Hall-voltage amplifier that produces an analog signal voltage Vsig having excursions of one polarity corresponding to the passing of magnetic articles. The gain... | 08/08/2000 |
| 6051997 | Circuit for tracking rapid changes in mid-point voltage of a data signal A circuit (11) for tracking rapid changes in peak and trough voltages of a data signal includes a peak detector circuit (13) and a trough detector circuit (14) coupled to the input for detecting peaks and troughs in the data signal and providing a peak an... | 04/18/2000 |
| 5939902 | Integrating circuit internally included in semiconductor device An integrating circuit internally included in a semiconductor device includes a constant voltage circuit 11 for generating a predetermined constant voltage VREF, and a voltage-to-current converting circuit 12 for converting the voltage VREF into a constan... | 08/17/1999 |
| 5805460 | Method for measuring RF pulse rise time, fall time and pulse width A method for measuring the rise/fall time and pulse width of RF pulses using multi-purpose, commercial-off-the-shelf test devices, such as an RF signal down converter, a digitizer and a signal processor. The method is based on digitizing the RF signals an... | 09/08/1998 |
| 5680066 | Signal transition detector circuit A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2)... | 10/21/1997 |
| 5566130 | Address transition detection (ATD) circuit for asynchronous VLSI chips A logic filtered address transition detection circuit that receives a chip select signal and an ATD pulse, and which produces an internal clock pulse using: an AND gate, a filtered input terminal, a delay unit and a comparator unit. The AND gate outputs a... | 10/15/1996 |
| 5559461 | Drive circuit detecting slow signal transition A drive circuit includes first and second circuit sections. The first circuit section maintains, during an initial stage of a transient period of an input signal, its output level before the signal transition and supplies after the transient period an out... | 09/24/1996 |
| 5513209 | Resampling synchronizer of digitally sampled signals A digital resampling system is provided for converting a first digital signal to a second digital signal, where both signals represent the same analog signal but sampled at two different clock rates which are not phase-locked together. A filter is clocked... | 04/30/1996 |
| 5448529 | High speed and hierarchical address transition detection circuit An address transition detection (ATD) circuit provides an address transition detection pulse in response to either a high-to-low or low-to-high external address transition. The ATD circuit includes an address buffer that translates an externally applied a... | 09/05/1995 |
| 5418820 | Automatic polarity detection and correction method and apparatus employing linkpulses An apparatus and method for a transition detector and pulse width qualifying circuit for a differential receiver. The circuit generates pulses at every transition of a differential input signal and asserts a time-out signal upon detection of an end-of-tra... | 05/23/1995 |
| 5394035 | Rate of change comparator A rate of change comparator uses an RC charging circuit and a separate RC discharging circuit to follow a transducer output. The resistor component of each RC circuit is shunted by a diode, each biased in a different orientation so that the charging circu... | 02/28/1995 |
| 5378946 | Arrangement for temporal detection of a signal edge of an electrical signal transmitted over a transmission line Two edge detectors (12, 13) at the input (10.1) and the output (10.2) of a delay line (10) of the edge detector arrangement (11) generate detection signals of identical shape at the detected signal edges of a signal traveling over the delay line. The dela... | 01/03/1995 |
| 5374894 | Transition detection circuit A circuit for detecting the transition of the state of logic signals at a plurality of input terminals is provided. The circuit has a transition detecting block connected to each input terminal which generates a pulse at the transition of a logic signal a... | 12/20/1994 |
| 5357480 | Address change detecting system for a memory An address change detection system detects a change in an address input in a memory to initiate a read or write operation. The address change detection system uses a transition detection delay unit for each address bit of the memory. The transition detect... | 10/18/1994 |
| 5319607 | Semiconductor unit The present invention relates to a semiconductor unit including a delay circuit used for an address transition detecting circuit in a storage, wherein a change of an address is detected and, accordingly, an access address in a memory cell is altered. The ... | 06/07/1994 |
| 5319251 | Circuit arrangement for generating a switching pulse from a square-wave signal A circuit arrangement for generating a switching pulse in dependence upon an edge of a square-wave signal is proposed. The circuit arrangement includes a switch (T1) which is controlled by the square-wave signal and lies in a current path between a supply... | 06/07/1994 |
| 5313435 | Semiconductor memory device having address transition detector An address transition detector (ATD) of a semiconductor memory device. In particular, even if the address transition of the semiconductor memory device occurs over a long time, malfunction is prevented by synchronizing outputs of a buffer and a decoder an... | 05/17/1994 |
| 5313120 | Address buffer with ATD generation An address buffer (20) provides an ATD pulse in response to an address signal transitioning from one logic state to another. The address buffer (20) includes a differential amplifier (22), an emitter-follower transistor (35), and two P-channel transistors... | 05/17/1994 |
