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| Number | Title | Issue Date |
| 8415982 | Semiconductor integrated circuit device A semiconductor integrated circuit device includes: a first inverter constituted by a first transistor configured to charge a charge point based on an input signal, and a second transistor configured to discharge a discharge point based on the input signal; a P-type... | 04/09/2013 |
| 8390329 | Method and apparatus to compensate for hold violations A method for controlling a hold buffer delay is provided. A control voltage is generated in response to a measurement of at least one of process variation, temperature variation, and supply voltage variation to compensate for a hold violation, and the delay of a buf... | 03/05/2013 |
| 8384438 | Single-to-differential conversion circuit and method A conversion circuit includes a first inverter having an input node configured to receive a single-ended signal and second and third inverters each having respective inputs coupled to an output of the first inverter. A fourth inverter has an input coupled to an outp... | 02/26/2013 |
| 7839175 | Local clock buffer (LCB) with asymmetric inductive peaking A Local Clock Buffer (LCB), an IC chip including registers, some of which may include master/slave latches, locally clocked by the LCB, e.g., providing a launch clock and a capture clock each with an identified critical edge. The LCB includes asymmetrically inductiv... | 11/23/2010 |
| 7830178 | Dynamic circuit The dynamic circuit includes: a dynamic node; an evaluation circuit for changing the charged state of the dynamic node according to a result of logic evaluation for a plurality of input signals; a control circuit for outputting a control signal of which the logic le... | 11/09/2010 |
| 7482840 | Semiconductor integrated circuit The semiconductor integrated circuit includes: a first transistor of a first conductivity type connected between a first power supply and an output node and turned ON according to a first clock to put the output node to a first logic level; a second transistor of a ... | 01/27/2009 |
| 7459940 | Local clock buffer (LCB) with asymmetric inductive peaking A Local Clock Buffer (LCB), an IC chip including registers, some of which may include master/slave latches, locally clocked by the LCB, e.g., providing a launch clock and a capture clock each with an identified critical edge. The LCB includes asymmetrically inductiv... | 12/02/2008 |
| 7429879 | Clock receiver circuit device, in particular for semi-conductor components A semi-conductor component with a receiver, in particular a clock receiver circuit device, as well as a receiver, in particular a clock receiver circuit device is disclosed. The clock receiver circuit device includes a first input adapted to be connected with a firs... | 09/30/2008 |
| 7365575 | Gated clock logic circuit A gated clock logic circuit includes a pulse generator and a precharged latch. The pulse generator generates a pulse signal in response to a clock signal, and the precharged latch generates a gated clock signal in response to the clock signal, the pulse signal, and ... | 04/29/2008 |
| 7355454 | Energy recovery boost logic A boost circuit is disclosed that includes a plurality of transistors connected between complementary phases of a clock signal. The boost circuit further includes a first electrical node connected between at least two of the plurality of transistors wherein the plur... | 04/08/2008 |
| 7348827 | Apparatus and methods for adjusting performance of programmable logic devices A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmab... | 03/25/2008 |
| 7346861 | Programmable logic devices with two-phase latch circuitry Programmable logic circuitry includes level-sensitive latches as at least some of the data storage elements. At least some of the latches are enabled by one phase of a clock signal, and at least some others of the latches are enabled by the other phase of the clock ... | 03/18/2008 |
| 7342568 | Shift register circuit A shift register circuit having shift registers comprising a first transistor having a gate and a first source/drain for receiving an output signal of a pre-stage shift register, a second transistor having a gate coupled to a second source/drain of the first transis... | 03/11/2008 |
| 7339403 | Clock error detection circuits, methods, and systems Clock error detections circuits can detect clock duty cycle error and/or quadrature phase error. During an evaluation phase, capacitors are charged. During an evaluation phase, the capacitors are unequally discharged based on the error. A positive feedback mechanism... | 03/04/2008 |
| 7336521 | Memory pumping circuit A memory pumping circuit is proposed. The feature of the present invention is the charging capacitor of the pumping circuit is a DRAM cell for enhancing the capacitance. ... | 02/26/2008 |
| 7323910 | Circuit arrangement and method for producing a dual-rail signal Circuit arrangement for producing a dual-rail output signal having a signal processing apparatus with two switches, which are driven as a function of an input signal, a first output connected via one of the switches to a signal processing apparatus foot point, which... | 01/29/2008 |
| 7317780 | Shift register circuit A shift registers circuit having a series of cascading shift registers comprises a first transistor coupling to an output signal of a pre-stage shift register, a second transistor coupling to the first transistor, an output and a first clock signal, and a pull-down ... | 01/08/2008 |
| 7313050 | Word-line driver for memory devices A word-line driver has an input from a word-line decoder and an output to drive a word-line. The word-line driver comprises a plurality of inverters connected in series between the input and output including a first and a second inverter with a first node designatin... | 12/25/2007 |
| 7301373 | Asymmetric precharged flip flop A flip-flop circuit includes a differential stage coupled to a latch stage. The differential stage comprises cross-coupled dynamic logic and only provides a single output to the latch stage. During an evaluation phase, the state of a data input signal is sensed. Dep... | 11/27/2007 |
| 7301372 | Domino logic compatible scannable flip-flop A testable, prechargeable circuit has a driving circuit for producing a driving circuit output signal. A timing circuit receives a clock signal and the driving circuit output signal to cause an output of the testable, prechargeable circuit to be in a low state when ... | 11/27/2007 |
| 7282960 | Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock A dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock controlled provides increased noise immunity in dynamic digital circuits. By clocking the pre-charge element with a signal having a reduced swing in the voltage... | 10/16/2007 |
| 7268590 | Method and apparatus for implementing subthreshold leakage reduction in LSDL A method and apparatus are provided for implementing subthreshold leakage current reduction in limited switch dynamic logic (LSDL). A limited switch dynamic logic circuit includes a cross-coupled NAND and inverter logic. A dynamic node provides a first input to the ... | 09/11/2007 |
| 7265585 | Method to improve current and slew rate ratio of off-chip drivers An off-chip driver (OCD) circuit and technique to reduce skew between rising and falling edges of output signals as process conditions vary are provided. Variations in process conditions may result in stronger or weaker relative current drive between NMOS and PMOS t... | 09/04/2007 |
| 7262631 | Method and apparatus for controlling a voltage level A voltage level control device operable to control a voltage level supplied from a first voltage level source to circuitry, said circuitry being arranged between said first voltage level source and a second voltage level source, said first and second voltage level s... | 08/28/2007 |
| 7259986 | Circuits and methods for providing low voltage, high performance register files Circuits and methods are provided to implement low voltage, higher performance semiconductor memory devices such as CMOS static random access memory (SRAM) or multi-port register files. For example, circuits and methods are provided for dynamically adjusting power s... | 08/21/2007 |
| 7250789 | Pseudo-CMOS dynamic logic with delayed clocks Structures and methods for pseudo-CMOS dynamic logic with delayed clocks are provided. A pseudo-CMOS dynamic logic circuit with delayed clocks includes a dynamic pseudo-nMOS logic gate and a dynamic pseudo-pMOS logic gate coupled thereto. The dynamic pseudo-nMOS log... | 07/31/2007 |
| 7245157 | Dynamic phase assignment optimization using skewed static buffers in place of dynamic buffers A primarily domino logic block uses static buffers instead of clocked domino buffers to correct a phase skipping problem, while realizing the same logic function with less integrated circuit area, power consumption, and cost. The use of static buffers simplifies the... | 07/17/2007 |
| 7224190 | Midcycle latch for power saving and switching reduction The present invention relates to the field of hardware logic circuits and in particular to dynamic hardware logic implemented in computer processors, and more particularly, to an integrated circuit comprising a dynamic logic function implementing a predetermined log... | 05/29/2007 |
| 7218160 | Semiconductor integrated circuit A semiconductor integrated circuit according to the present invention comprises a latch circuit, a retaining circuit, and a feedback circuit, wherein the latch circuit inputs therein an input data signal, a clock signal and a feedback signal and outputs an output da... | 05/15/2007 |
| 7218151 | Domino logic with variable threshold voltage keeper A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce the contentio... | 05/15/2007 |
| 7215154 | Maskable dynamic logic An apparatus and method provide logically controlled masking of one or more maskable data bits from a plurality of data bits that are input to a dynamic logic circuit. No masking logic and attendant delay penalty is coupled in the data path that is not needed for un... | 05/08/2007 |
| 7205805 | Adjusting power consumption of digital circuitry relative to critical path circuit having the largest propagation delay error A method and apparatus is disclosed for adjusting at least one of a supply voltage and a clocking frequency applied to digital circuitry of a computing device, wherein the digital circuitry comprises a plurality of critical path circuits and a corresponding pluralit... | 04/17/2007 |
| 7202704 | Leakage sensing and keeper circuit for proper operation of a dynamic circuit A method and apparatus for ensuring proper operation of a dynamic circuit is provided. A dynamic circuit instance has a plurality of outputs connected to a respective one of a plurality of leakage detector circuits. An output of each leakage detector circuit is conn... | 04/10/2007 |
| 7193434 | Semiconductor integrated circuit There is provided a high-performance semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a switch block for switching conne... | 03/20/2007 |
| 7190204 | Logical circuit A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit... | 03/13/2007 |
| 7184285 | DC-DC conversion circuit In order to restrict variations of an output voltage of a DC—DC conversion circuit using TFTs, in a boost-type, a second n-ch TFT N2 and a second p-ch TFT P2 are newly provided. With regard to the second n-ch TFT N2, a gate thereof is connecte... | 02/27/2007 |
| 7180332 | Clock synchronization circuit A clock synchronization circuit for synchronizing a first clock signal and a second clock signal for data transfer from a first function block, which is clocked by the first clock signal, to a second function block which is clocked by the second clock signal, where ... | 02/20/2007 |
| 7177192 | Method of operating a flash memory device A method of operating a NAND flash memory device that comprising a unit string comprising a string selection transistor connected to a bit line, a cell transistor connected to the string selection transistor, and a ground selection transistor connected to the cell t... | 02/13/2007 |
| 7173456 | Dynamic logic return-to-zero latching mechanism A dynamic logic return-to-zero (RTZ) latching mechanism including a complementary pair of evaluation devices responsive to a clock signal, a dynamic evaluator, delayed inversion logic, and latching logic. The dynamic evaluator is coupled between the complementary pa... | 02/06/2007 |
| 7164597 | Computer systems A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load electrode and a second electrode. The first load electrode is coupled to a first control line. The SRAM cell al... | 01/16/2007 |
