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| Number | Title | Issue Date |
| 8067954 | Fault tolerant integrated circuit architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element inter... | 11/29/2011 |
| 8035410 | Latch circuit A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchroniza... | 10/11/2011 |
| 7999567 | SEU tolerant arbiter Single Event Upset (SEU, also referred to as soft error) tolerant arbiters, bare arbiters, and filters are disclosed. An arbiter provides a filter section, and a bare arbiter, coupled to the filter section. The bare arbiter includes a redundant first input and a red... | 08/16/2011 |
| 7982489 | Resilient integrated circuit architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element inter... | 07/19/2011 |
| 7977965 | Soft error detection for latches A system and method for soft error detection in digital ICs is disclosed. The system includes an observing circuit coupled to a latch, which circuit is capable of a response upon a state change of the latch. The system further includes synchronized clocking provided... | 07/12/2011 |
| 7948260 | Method and apparatus for aligning the phases of digital clock signals A method and apparatus for aligning the phases of digital clock signals are disclosed. For example, a phase alignment circuit according to one embodiment includes a frequency adjuster comprising a first plurality of inputs, where at least some of the first plurality... | 05/24/2011 |
| 7898284 | Asynchronous nano-electronics Asynchronous nanoelectronic circuits that operate according to principles of quasi-delay insensitive design are described. Circuit or logic elements comprising n-type devices are fabricated in a first n-plane, p-type devices are fabricated in a p-plane, and connecti... | 03/01/2011 |
| 7888959 | Apparatus and method for hardening latches in SOI CMOS devices A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor i... | 02/15/2011 |
| 7880497 | Fault tolerant integrated circuit architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element inter... | 02/01/2011 |
| 7812630 | Latch circuit A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchroniza... | 10/12/2010 |
| 7812629 | Resilient integrated circuit architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element inter... | 10/12/2010 |
| 7800396 | Semiconductor integrated circuit, control method, and information processing apparatus A semiconductor integrated circuit includes a circuit block connected to an arithmetic processing unit via a bus, a power supply noise data generator which is configured to generate a power supply noise data signal by converting power supply noise generated in power... | 09/21/2010 |
| 7795900 | Memory array with multiple-event-upset hardening An integrated circuit has a memory array with a four-plex of SEU-hardened memory cells. Each of the SEU-hardened memory cells has an orientation different from each of the other SEU-hardened memory cells in the four-plex, and each of the SEU-hardened memory cells ha... | 09/14/2010 |
| 7741864 | Fault tolerant asynchronous circuits New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, such as the type introduced through radiation or, more broadly, single-event effects (SEEs). SEE-tolerant configurations are shown and described for combina... | 06/22/2010 |
| 7705624 | Fault tolerant integrated circuit architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element inter... | 04/27/2010 |
| 7626415 | Method and apparatus for configuring an integrated circuit A configuration management system is disclosed. For example, an embodiment of the present invention provides a configuration management system comprising a configuration storage device containing configuration data, and an integrated circuit, coupled to the configur... | 12/01/2009 |
| 7616024 | Resilient integrated circuit architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element inter... | 11/10/2009 |
| 7576557 | Method and apparatus for mitigating one or more event upsets A method of configuring an integrated circuit having programmable logic including the steps of generating a configuration bitstream in accordance with a configuration setup, storing the configuration bitstream into a portion of a memory, configuring the programmable... | 08/18/2009 |
| 7576558 | Apparatus and method for enhanced readback of programmable logic device state information A method and apparatus is provided to significantly increase the flexibility of readback capture mechanisms, the apparatus being an integrated circuit device, comprising a configuration data router coupled to receive at least one configuration data frame from a conf... | 08/18/2009 |
| 7550991 | Configurable IC with trace buffer and/or logic analyzer functionality Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits for configurably performing different operations and several user design state (UDS) circuits for storing user-design state values. The IC fu... | 06/23/2009 |
| 7548084 | Fault tolerant integrated circuit architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element inter... | 06/16/2009 |
| 7504850 | Single-event-effect tolerant SOI-based inverter, NAND element, NOR element, semiconductor memory device and data latch circuit Disclosed is an inverter, a NAND element, a NOR element, a memory element and a data latch circuit which exhibit high tolerance to single event effect (SEE). In an SEE tolerant inverter (3I), each of a p-channel MOS transistor and a n-channel MOS transistor w... | 03/17/2009 |
| 7504851 | Fault tolerant asynchronous circuits New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combina... | 03/17/2009 |
| 7474116 | Latch circuit A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchroniza... | 01/06/2009 |
| 7443191 | Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the rou... | 10/28/2008 |
| 7429870 | Resilient integrated circuit architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element inter... | 09/30/2008 |
| 7427871 | Fault tolerant integrated circuit architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element inter... | 09/23/2008 |
| 7423448 | Radiation hardened logic circuit A radiation-hardened logic circuit prevents SET-induced transient pulses from propagating through the circuit, using two identical logic paths. The outputs of the two logic paths are fed into an exclusive-OR gate, which controls gating circuitry. The gating circuitr... | 09/09/2008 |
| 7411412 | Semiconductor integrated circuit A semiconductor integrated circuit including: N modules set in their functions in accordance with input function setting data, a circuit block having R number of I/O parts, and a module selection part for selecting R number of modules from among the N number of modu... | 08/12/2008 |
| 7411411 | Methods and systems for hardening a clocked latch against single event effects Methods and systems for hardening a clocked latch against single event effects are disclosed. A system includes a first three-input OR gate, a first NAND gate, a second three-input OR gate, and a second NAND gate. The first three-input OR gate receives as inputs a c... | 08/12/2008 |
| 7405990 | Method and apparatus for in-system redundant array repair on integrated circuits Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit wit... | 07/29/2008 |
| 7397709 | Method and apparatus for in-system redundant array repair on integrated circuits Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit wit... | 07/08/2008 |
| 7397268 | Receiver circuit In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predet... | 07/08/2008 |
| 7397269 | Disconnection and short detecting circuit that can detect disconnection and short of a signal line transmitting a differential clock signal Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal input... | 07/08/2008 |
| 7386826 | Using redundant routing to reduce susceptibility to single event upsets in PLD designs Methods of implementing designs in programmable logic devices (PLDs) to reduce susceptibility to single-event upsets (SEUs) by taking advantage of the fact that most PLD designs leave many routing resources unused. The unused routing resources can be used to provide... | 06/10/2008 |
| 7375544 | Semiconductor apparatus having logic level decision circuit and inter-semiconductor apparatus signal transmission system In a signal transmission system between a plurality of semiconductor apparatuses, a logic level decision circuit deciding a logic level of an input signal in accordance with which of two reference signals a signal level of the input signal is close to, by using two ... | 05/20/2008 |
| 7368935 | Tamper response system for integrated circuits A tamper response system to protect intellectual property is provided. In one embodiment, the tamper response system includes at least one sensor adapted to sense tamper activity and a tamper circuit. The tamper circuit is coupled to receive tamper signals from the ... | 05/06/2008 |
| 7365565 | Programmable system on a chip for power-supply voltage and current monitoring and control A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip... | 04/29/2008 |
| 7362121 | Self-heating mechanism for duplicating microbump failure conditions in FPGAs and for logging failures A system replicates the rapid temperature increases that are believed to cause microbump failures in certain applications of programmable logic devices (PLDs). The system configures a PLD under test with a circuit that switches a large amount of current and generate... | 04/22/2008 |
| 7358765 | Dedicated logic cells employing configurable logic and dedicated logic functions A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic functio... | 04/15/2008 |
