Did You Know...
...that the Slinky toy was the result of a failed attempt by engineer Richard James to produce an antivibration device for ship instruments? His goal was to develop a spring that would instantaneously counterbalance the wave motion that rocks a ship at sea. Instead, he developed the Slinky.
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| Number | Title | Issue Date |
| 7843219 | XOR logic circuit An XOR logic circuit includes a first transfer unit configured to transfer a logic high level data to an output terminal in response to data applied to first and second input terminals; a multiplexing unit configured to output a power voltage or a ground voltage in ... | 11/30/2010 |
| 7755390 | XOR logic circuit An XOR logic circuit includes a first transfer unit configured to transfer a logic high level data to an output terminal in response to data applied to first and second input terminals; a multiplexing unit configured to output a power voltage or a ground voltage in ... | 07/13/2010 |
| 7750677 | CMOS back-gated keeper technique A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such bo... | 07/06/2010 |
| 7557614 | Topology for a n-way XOR/XNOR circuit A method for configuring a n-way XOR/XNOR circuit comprises providing a plurality of top stacks of PFETs each including at least three PFETs electrically connected between a high logic level and an output logic connection, providing a plurality of bottom stacks of N... | 07/07/2009 |
| 7365576 | Binary digital latches not using only NAND or NOR circuits A switching model to create stable binary sequential devices comprised of one or more logic functions with feedback of which an output signal is uniquely related to an input signal is applied to possible binary logic functions. Static latches of commutative and non-... | 04/29/2008 |
| 7362646 | Semiconductor memory device A semiconductor memory device includes a memory cell array provided in a cell array area and including a plurality of memory cells, a source potential line which applies a source potential to the memory cells, a switching element group provided in the cell array are... | 04/22/2008 |
| 7358769 | XOR circuit An XOR circuit designed in dual rail includes four shunt transistors, wherein the shunt transistors are disposed to couple an input potential at a first input or a second input with an output. ... | 04/15/2008 |
| 7312634 | Exclusive-or and/or exclusive-nor circuits including output switches and related methods An exclusive-OR circuit may include a NAND gate configured to receive a plurality of input signals and a NOR gate configured to receive the plurality of input signals. The exclusive-OR circuit may also include a switch configured to couple an output signal of the NA... | 12/25/2007 |
| 7298171 | Layout area efficient, high speed, dynamic multi-input exclusive or (XOR) and exclusive NOR (XNOR) logic gate circuit designs for integrated circuit devices A layout area efficient, high speed, dynamic multi-input exclusive OR (XOR) and exclusive NOR (XNOR) logic gate circuit design of especial utility with respect to integrated circuit devices. The logic gate design disclosed herein utilizes fewer transistors than trad... | 11/20/2007 |
| 7285987 | Self DC-bias high frequency logic gate, high frequency NAND gate and high frequency NOR gate A self DC-bias high frequency logic gate is disclosed. The logic gate comprises at least one input terminal and one output terminal for performing Boolean operation on the high frequency input signals. The logic gate is characterized in that each transistor is coupl... | 10/23/2007 |
| 7279936 | Logic basic cell, logic basic cell arrangement and logic device A logic basic cell, a logic basic cell arrangement, and a logic device. A logic basic cell is provided for forming a logic combination of two data signals in accordance with a logic function that can be selected by means of a plurality of logic selection elements, h... | 10/09/2007 |
| 7271703 | 2-bit binary comparator and binary comparing device using the same A 2-bit binary comparator, including: a comparison unit for receiving a first bit and a second bit to thereby compare the first bit with the second bit; and an enable unit for outputting a comparison result of the comparison unit as an output of the 2-bit binary com... | 09/18/2007 |
| 7242219 | Circuit for parity tree structure A circuit for a parity tree is disclosed. In one embodiment, a circuit for a parity tree includes a pull-up circuit, a pull-down circuit, and a cross-couple circuit. The circuit, an XOR/XNOR circuit, includes both an output node and an inverted output node. For a gi... | 07/10/2007 |
| 7218153 | Word line driver with reduced leakage current A circuit system having a first inverter, a second inverter and a blockage module is disclosed. The first inverter is coupled between a supply voltage and a complementary input signal, for generating a first output signal on an output terminal thereof in response to... | 05/15/2007 |
| 7215142 | Multi-stage inverse toggle An inverse toggle circuit includes a pair of input connections for receiving each of four possible input signal combinations in a sequential rotational manner. Each of four data paths are defined to be exercised in accordance with a respective input signal combinati... | 05/08/2007 |
| 7199573 | Electronic circuit with test unit A test arrangement for testing the interconnections of an electronic circuit (100) and a further electronic circuit is provided. A first selection of I/O nodes (120), which are arranged to receive input data in a functional mode of the electronic circu... | 04/03/2007 |
| 7142014 | High frequency XOR with peaked load stage An apparatus and method of the present invention includes a high frequency exclusive OR (XOR) with a peaked load stage. The peaked load stage coupled to the XOR produces a peaked response at a specified frequency of operation. The high frequency XOR comprises a mixe... | 11/28/2006 |
| 7142669 | Circuit for generating hash values A Message Digest Hardware Accelerator (MDHA) 10 for implementing multiple cryptographic hash algorithms such as the Secure Hashing Algorithm 1 (SHA-1), the Message Digest 4 (MD4) algorithm and the Message Digest 5 (MD5) algorithm. A register file (12) ... | 11/28/2006 |
| 7088138 | Symmetric and non-stacked XOR circuit A CML XOR logic circuit is provided that includes a pair of pull-up transistors, a pair of current source transistors and a logic switch network coupled between the pull-up transistors and the current source transistors. The logic switch network including a pluralit... | 08/08/2006 |
| 7075335 | Level shifter A first and a second semiconductor switching elements are provided in parallel between a first supply voltage and a second negative reference voltage to become conductive based on an input signal. A first and a second high breakdown voltage semiconductor switching e... | 07/11/2006 |
| 7030658 | Systems and methods for operating logic circuits Systems and methods for reducing the power consumption of some combinations of logic gates by reducing the number of unnecessary transitions that are made by logic gates that do not affect the output of the logic. In one embodiment, a modified exclusive-OR (XOR) gat... | 04/18/2006 |
| 7005695 | Integrated circuitry including a capacitor with an amorphous and a crystalline high K capacitor dielectric region The invention comprises integrated circuitry and to methods of forming capacitors. In one implementation, integrated circuitry includes a capacitor having a first capacitor electrode, a second capacitor electrode and a high K capacitor dielectric region received the... | 02/28/2006 |
| 6930512 | One-level zero-current-state exclusive or (XOR) gate Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transist... | 08/16/2005 |
| 6909659 | Zero power chip standby mode A zero power standby mode in a memory device used in a system, such as a battery powered hand held device. By disconnecting the internal power supply bus on the memory device from the external power supply during standby mode, the junction leakage and gate induced d... | 06/21/2005 |
| 6803793 | Reduced swing charge recycling circuit arrangement and adder including the same A circuit arrangement uses differential pass transistor logic, a low voltage swing and charge recycling to save power, in which the swing voltage is reduced, but the supply voltage is not reduced, thereby maintaining the transistor device current and avoiding speed ... | 10/12/2004 |
| 6781412 | Logic circuit for fast carry/borrow Each binary carry logic circuit 20 of half adder circuits other than that for the least significant digit comprises a transfer gate 212 turned on when an input bit A2 is active and receiving a carry-in bit *C2 at its data input, and a tra... | 08/24/2004 |
| 6765410 | Method and apparatus for performing a hazard-free multi-bit comparison An exclusive OR (XOR) circuit is provided to perform a logical XOR function on multiple bits that eliminates the XOR function hazard. The XOR circuit performs a logical XOR function on data values that have been encoded to prevent the XOR function hazard from occurr... | 07/20/2004 |
| 6727728 | XOR circuit An XOR circuit includes XOR function logic. One advantage of the XOR circuit is that the complements of A and B are not required. The XOR circuit receives an enable signal that disables all the load transistors to eliminate static power dissipation of the XOR circui... | 04/27/2004 |
| 6724221 | Circuitry having exclusive-OR and latch function, and method therefor In one form of the invention, circuitry having exclusive-OR and latch functionality includes timing circuitry and logic circuitry. The circuitry includes a memory, with first and second memory nodes, for storing a state and its complement, and first and second timin... | 04/20/2004 |
| 6700405 | Logic circuit and full adder using the same A logic circuit capable of suppressing occurrence of wraparound of signals, capable of reducing power consumption, and in addition achieving a reduction of a circuit scale and an improvement of an operating speed and a full adder using the same, wherein p... | 03/02/2004 |
| 6686776 | Digital data coincidence determining circuit A coincidence determining circuit determines whether first and second digital data each consisting of a plurality of bits coincide with one another. The coincidence determining circuit includes a wiring and a plurality of bit comparison circuits correspon... | 02/03/2004 |
| 6680625 | Symmetrical CML logic gate system High speed CML logic gate systems for providing selected Boolean logic functions. Two halves of a substantially symmetric first system, having a relatively small number (14) of CMOS transistors, are used to generate any of the logic functions AND, NAND, O... | 01/20/2004 |
| 6549037 | Apparatus and circuit having reduced leakage current and method therefor Briefly, in accordance with one embodiment of the invention, an integrated circuit comprises a first stage that provides differential outputs in one mode and substantially equal outputs in another mode.... | 04/15/2003 |
| 6456116 | Dynamic comparator circuit In one embodiment, the present invention provides a multi-bit dynamic comparator for comparing first and second words having a plurality of comparative bit pairs with each pair having comparative first and second word bits. The multi-bit comparator includ... | 09/24/2002 |
| 6242951 | Adiabatic charging logic circuit An adiabatic charging logic circuit includes a logic circuit and a power supply section. The logic circuit is constituted by a plurality of logic elements. The power supply section supplies power to the logic circuit to cause the logic circuit to perform ... | 06/05/2001 |
| 6194917 | XOR differential phase detector with transconductance circuit as output charge pump An apparatus for and method of reducing transistor body effect when detecting and correcting a phase error between clock signals using delay-locked and phase-locked loop circuits. The clock signals are provided to an equal number of circuit elements in cr... | 02/27/2001 |
| 6137309 | Exclusive-or logic gate with four two-by-two complementary inputs and two complementary outputs, and frequency multiplier incorporating said gate An Exclusive-OR logic gate with four two-by-two complementary inputs and two complementary outputs. The structure of this Exclusive-Or gate is said to be symmetrical in that the gate has a propagation time that is identical whichever of the two pairs of c... | 10/24/2000 |
| 6133752 | Semiconductor integrated circuit having tri-state logic gate circuit The tri-state logic gate circuit is preferably made up of a first inverter circuit which selectively outputs one of the power supply voltage and a ground potential, a second inverter circuit which selectively outputs one of the first inverter circuit outp... | 10/17/2000 |
| 6118305 | Semiconductor integrated circuit capable of preventing breakdown of a gate oxide film The present invention provides a semiconductor integrated circuit comprising a plurality of logic circuits, each of which has at least a first field effect transistor with a first gate connected to a high voltage line and at least a second field effect tr... | 09/12/2000 |
| 6087850 | Operation circuit The first store unit (R1) for receiving and storing the first input (AI), the second store unit (R2) for receiving and storing the second input (BI), a selection unit (SEL) for selecting one of outputs from the first inverter (IV1) and the second inverter... | 07/11/2000 |
