Did You Know...
...that Robert Adler has the dubious distinction of being the Father of the Couch Potato? Back in 1955 Adler was employed by what was then Zenith Radio Corp., where he was charged to invent something that would allow viewers to turn down the TV volume without leaving their chairs. After a series of flops (such as a wired contraption that people tripped over), Adler hit on the idea of using sound waves. Thus the Remote Control was born...
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| Number | Title | Issue Date |
| 8115513 | Circuits for soft logical functions A circuit implementing a soft logical processing network includes an interconnection of analog processing elements, which can include soft logic gates, the soft logic gates including one or more soft logic gates. In some examples, each of the soft logic gates includ... | 02/14/2012 |
| 8058903 | Apparatus for providing a combined digital signal An apparatus for providing a combined digital signal comprises a bit adder and a combiner. The combined digital signal contains information of a first digital input signal and a second digital input signal, wherein a block length of the first digital input signal is... | 11/15/2011 |
| 8030963 | Integrated circuit and standard cell for an integrated circuit In one embodiment, a cell of an integrated circuit includes a master-slave flip-flop and comparator logic having inputs adapted to receive an input signal of the master-slave flip-flop, an inverted input signal of the master-slave flip-flop, an output signal of the ... | 10/04/2011 |
| 7560955 | Logic circuit Disclosed is a logic circuit including first and second input terminals, supplied with respective logic signals, and first and second MOS transistors, having sources respectively connected to associated ones of the first and second input terminals and gates cross-co... | 07/14/2009 |
| 7554359 | Circuit for inspecting semiconductor device and inspecting method It is configured by plurality of NAND circuits connected in series through a plurality of inverters, and a plurality of NOR circuits connected in series through the plurality of inverters. Each of a plurality of source signal lines provided in a pixel portion is con... | 06/30/2009 |
| 7439770 | Magnetic tunneling junction based logic circuits and methods of operating the same MTJ cell based logic circuits and MTJ cell drivers having improved operating speeds compared to the conventional art, and operating methods thereof are described. An MTJ cell driver may include a lower electrode, an MTJ cell on the lower electrode, an upper electrod... | 10/21/2008 |
| 7429872 | Logic circuit combining exclusive OR gate and exclusive NOR gate A logic circuit combining an exclusive OR gate and an exclusive NOR gate is provided. The logic circuit includes an NMOS transistor, a PMOS transistor, and first and second inverters. The NMOS transistor has a source connected to a first input signal, a drain connec... | 09/30/2008 |
| 7408482 | Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data in... | 08/05/2008 |
| 7403043 | Magnetic Transistor Circuit Representing the Data ‘1’ and ‘0’ of the Binary System A magnetic transistor circuit representing the data ‘1’ and ‘0’ of the binary system comprises a routing line and a magnetic transistor unit. The routing line has a current going through with a first current direction or a second current direction, wherein t... | 07/22/2008 |
| 7397277 | Magnetic transistor circuit with the EXOR function A magnetic transistor circuit has a first and a second magnetic transistor. These two magnetic transistors that work as the ordinary transistors can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transist... | 07/08/2008 |
| 7372296 | Configurable logic device providing enhanced flexibility, scalability and providing area efficient implementation of arithmetic operation on n-bit variables The configurable logic device provides enhanced flexibility, scalability and area efficient implementation of arithmetic operation on (N−1) bit variables. The device includes a first configurable logic subsystem capable of generating logic OR output in response to... | 05/13/2008 |
| 7355457 | Frequency synthesizer The invention relates to a frequency synthesizer. An object of the invention is to provide a frequency synthesizer whose high stable performance is realized at an inexpensive cost. The frequency synthesizer includes a frequency synthesizing section generating an out... | 04/08/2008 |
| 7355445 | Digital circuit with smaller amplitude of input signal voltage than amplitude of power source voltage of the digital circuit In order to provide a semiconductor device having a circuit for operating normally even when the amplitude of a signal voltage is smaller than the amplitude of a power source voltage, a correcting circuit is provided before a digital circuit to be operated normally.... | 04/08/2008 |
| 7342579 | Thin film transistor array plate, liquid crystal display panel and method of preventing electrostatic discharge A thin film transistor array plate, a liquid crystal display panel and a method of preventing electrostatic discharge thereof are provided. The thin film transistor array comprises a substrate, pixel structures, switching devices, lead lines and electrostatic discha... | 03/11/2008 |
| 7327356 | Data transmission device and data transmission method The data transmission device transmits parallel data of a plurality of bits. The data transmission device includes a parallel data control unit that outputs parallel data for which the logic level of each bit of the parallel data is inverted when the number of bits ... | 02/05/2008 |
| 7312634 | Exclusive-or and/or exclusive-nor circuits including output switches and related methods An exclusive-OR circuit may include a NAND gate configured to receive a plurality of input signals and a NOR gate configured to receive the plurality of input signals. The exclusive-OR circuit may also include a switch configured to couple an output signal of the NA... | 12/25/2007 |
| 7279936 | Logic basic cell, logic basic cell arrangement and logic device A logic basic cell, a logic basic cell arrangement, and a logic device. A logic basic cell is provided for forming a logic combination of two data signals in accordance with a logic function that can be selected by means of a plurality of logic selection elements, h... | 10/09/2007 |
| 7269061 | Magnetic memory A magnetic memory has a first, a second and a third magnetic transistor. The first magnetic transistor has a first magnetic section and a second magnetic section, wherein the first magnetic section couples to a high voltage end. The second magnetic transistor has a ... | 09/11/2007 |
| 7256616 | Magnetic transistor with the buffer/inverter functions A magnetic transistor circuit has a first and a second magnetic transistor. These two magnetic transistors that work as the ordinary transistors can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transist... | 08/14/2007 |
| 7245164 | Radio frequency doubler When a signal of a double frequency is generated from the original signal, conventionally a 90-degree phase-shift circuit is necessary to suppress an output of a DC component and efficiently obtain a double wave. According to the present invention, an equal RF signa... | 07/17/2007 |
| 7242634 | Pseudo-dynamic word-line driver In certain embodiments, the present invention is a word-line driver for an address decoder that decodes a multi-bit address to enable access to a row of circuit elements such as memory cells in a block of memory implemented in a dedicated memory device or as part of... | 07/10/2007 |
| 7242219 | Circuit for parity tree structure A circuit for a parity tree is disclosed. In one embodiment, a circuit for a parity tree includes a pull-up circuit, a pull-down circuit, and a cross-couple circuit. The circuit, an XOR/XNOR circuit, includes both an output node and an inverted output node. For a gi... | 07/10/2007 |
| 7231572 | Method and circuit for parametric testing of integrated circuits with an exclusive-or logic tree A circuit for parametric testing of an integrated circuit includes an integrated circuit having a plurality of input buffers and a plurality of XOR gates. The plurality of XOR gates have a first input that is connected to an output of one of the input buffers and ha... | 06/12/2007 |
| 7222202 | Method for monitoring a set of semaphore registers using a limited-width test bus Certain embodiments of the invention may be found in a method and system for monitoring a set of semaphore registers using a limited-width test bus. Each semaphore register represents a separate hardware resource. The bits in a semaphore register are monitored joint... | 05/22/2007 |
| 7218139 | Programmable integrated circuit providing efficient implementations of arithmetic functions Efficient implementations of arithmetic functions in programmable ICs include carry chain multiplexers driven by dual-output programmable function generators. A function generator having two output signals is programmed to generate both an exclusive OR (XOR) functio... | 05/15/2007 |
| 7205795 | Semiconductor device having universal logic cell A universal logic module includes: a first inverter outputting an inverted input signal to an output terminal through a first transfer gate, the inverted input signal having an inverted level of an input signal provided from a first input terminal; and a second inve... | 04/17/2007 |
| 7203714 | Logic circuit A CMOS logic circuit is disclosed wherein the number of kinds of basic parts is suppressed to five to allow designing of a circuit which operates at a high speed and repetitiveness of wiring lines is increased to allow designing of a circuit which is simple in circu... | 04/10/2007 |
| 7187204 | Circuit for inspecting semiconductor device and inspecting method It is configured by plurality of NAND circuits connected in series through a plurality of inverters, and a plurality of NOR circuits connected in series through the plurality of inverters. Each of a plurality of source signal lines provided in a pixel portion is con... | 03/06/2007 |
| 7170317 | Sum bit generation circuit Sum bit generation circuit includes first logic generating first signal as XOR of first and second input signals and second signal as the inverse of XOR of the first and second input signals; second logic receiving the first and second signals generated by first log... | 01/30/2007 |
| 7142021 | Data inversion circuits having a bypass mode of operation and methods of operating the same An integrated circuit device includes a data inversion circuit configured to support an inversion mode of operation. The inversion mode of operation inverts selected ones of a plurality of N-bit words received in consecutive sequence at inputs thereof. The data inve... | 11/28/2006 |
| 7123071 | Method and device for producing delayed signals In order to generate an output signal delayed compared to an input signal and with a defined mark-to-space ratio, it is useful to produce at least first and second intermediate signals delayed differently with respect to the input signal and to combine them to form ... | 10/17/2006 |
| 7117428 | Redundancy register architecture for soft-error tolerance and methods of making the same A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whet... | 10/03/2006 |
| 7064583 | Arbiters with preferential enables for asynchronous circuits One embodiment of the present invention provides a circuit that preferentially grants requests. This circuit monitors at least two inputs for request signals and at least two inputs for enable signals, wherein each request signal is associated with a corresponding e... | 06/20/2006 |
| 6998877 | High speed differential signaling logic gate and applications thereof A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, current source, a 1st load, and a 2nd load. The 1st input transistor is operably co... | 02/14/2006 |
| 6992506 | Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data in... | 01/31/2006 |
| 6975546 | Signal line driver circuit which reduces power consumption and enables high-speed data transfer A signal line drive circuit is capable of reducing the charge consumption in a circuit device, and further, transferring data at high speed. A determination circuit determines whether the present signals of a first signal line and a second signal line are the same o... | 12/13/2005 |
| 6934308 | Precoding circuit and precoding-mulitplexing circuit for realizing very high transmission rate in optical fiber communication A precoding-multiplexing circuit is formed by a precoding circuit for carrying out a precoding with respect to n sets of parallel input binary data signals having a bit rate equal to R/n, to obtain n sets of parallel precoded signals, and a time division multiplexer... | 08/23/2005 |
| 6822885 | High speed latch and compare function A high speed latch and compare function providing rapid cache comparison through the use of a dual rail comparison circuit having transmission gate exclusive or (XOR) circuits. ... | 11/23/2004 |
| 6819142 | Circuit for transforming a differential mode signal into a single ended signal with reduced standby current consumption An apparatus for converting a differential mode signal into a single ended signal with reduced power consumption. A preferred embodiment comprises a single ended converter (for example, a single ended converter 505) and an output transistor (for example, outp... | 11/16/2004 |
| 6788106 | Integrated circuit devices having data inversion circuits therein that reduce simultaneous switching noise and support interleaving of parallel data Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data in... | 09/07/2004 |
