Did You Know...
...In 1790, the cost to obtain a patent was between $4 and $5.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7432736 | Logic basic cell A logic basic cell contains a first logic function block and a second logic function block for the logic combination of a first input signal and a second input signal in accordance with a predeterminable first or second logic subfunction, and a first logic transisto... | 10/07/2008 |
| 7430137 | Non-volatile memory cells in a field programmable gate array A non-volatile memory cell comprises a first floating gate transistor having a source, a drain, and a gate electrically coupled to a row line. A second floating gate transistor has a source, a drain, and a gate electrically coupled to the row line. A first p-channel... | 09/30/2008 |
| 7369443 | Semiconductor device with adjustable signal drive power A semiconductor device includes a terminal configured to receive a first signal that is set from an exterior at a time of operation, a memory unit configured to retain a state of a setting fixedly regardless of whether at the time of operation or at a time of no ope... | 05/06/2008 |
| 7366032 | Multi-ported register cell with randomly accessible history A multi-ported register cell. The register cell includes a base cell and a plurality of history cells, each of which is coupled to the base cell. Each of the plurality history cells is coupled to write to the base cell through a first port, and each of the plurality... | 04/29/2008 |
| 7355437 | Latch-up prevention circuitry for integrated circuits with transistor body biasing An integrated circuit such as a programmable logic device integrated circuit is provided that contains body-biased metal-oxide-semiconductor transistors and latch-up prevention circuitry to prevent latch-up from occurring in metal-oxide-semiconductor transistors. Bo... | 04/08/2008 |
| 7355440 | Method of reducing leakage current using sleep transistors in programmable logic device A programmable logic device (PLD) having minimal leakage current for inactive logic blocks is provided. The PLD includes an array of logic blocks. Among the array of logic blocks, one of the array of logic blocks monitors the level of activity of each of the remaini... | 04/08/2008 |
| 7348827 | Apparatus and methods for adjusting performance of programmable logic devices A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmab... | 03/25/2008 |
| 7321603 | Method and system for reducing bit error rate in a high-speed four to one time domain multiplexer Method and system for reducing bit error rate (BER) in a high-speed four-to-one time domain multiplexer are disclosed. In one embodiment of the present invention, a keep-alive current is employed in the latches of a four-to-one multiplexer in order to minimize the B... | 01/22/2008 |
| 7295036 | Method and system for reducing static leakage current in programmable logic devices A programmable logic device having logic block that can be selectively placed in a reduced power consumption mode is provided. The PLD includes a plurality of logic array blocks (LABs) and a plurality of interconnects defining signal pathways between the plurality o... | 11/13/2007 |
| 7279932 | Semiconductor integrated circuit device A semiconductor integrated circuit device has an electrically rewritable non-volatile memory that operates with a first power supply, and a second circuit that operates with a second power supply having a voltage lower than the voltage of the first power supply. The... | 10/09/2007 |
| 7256608 | Method and apparatus for reducing leakage in integrated circuits An efficient design methodology in accordance with the present invention is described for reducing the leakage power in CMOS circuits. The method and apparatus in accordance with the present invention yields better leakage reduction as the threshold voltage decrease... | 08/14/2007 |
| 7253662 | Method for forming an electric device comprising power switches around a logic circuit and related apparatus A method for forming an electric device having power switches around a logic circuit including: forming a logic circuit on a substrate; forming a plurality of power switches around the logic circuit; and coupling first ends of the power switches to a voltage end, an... | 08/07/2007 |
| 7249213 | Memory device operable with a plurality of protocols with configuration data stored in non-volatile storage elements An improved memory device is operable in a plurality of protocols. The improved memory device has an interface circuit which receives communication signals from a communication bus. The interface circuit decodes the communication signals and generates a plurality of... | 07/24/2007 |
| 7248080 | Power supply switching at circuit block level to reduce integrated circuit input leakage currents Leakage currents at IC inputs can be avoided while the IC is disabled by providing a switch that is responsive to deactivation of an enable input to isolate functional circuitry of the IC from one of the power supply nodes of the IC. This eliminates power supply cur... | 07/24/2007 |
| 7239175 | Look-up table based logic macro-cells A programmable look up table (LUT) structure of an integrated circuit, comprising: two or more LUT circuits, each said LUT circuit comprising: one or more inputs; and a plurality of LUT values; and at least one output; and a configurable multiplexer (MUX) circuit co... | 07/03/2007 |
| 7221192 | Voltage access circuit configured for outputting a selected analog voltage signal for testing external to an integrated circuit Access is provided to internal analog voltage signals on internal analog nodes of an integrated circuit, without distortion of the internal analog voltage signals. An integrated circuit includes a voltage access circuit having buffered multiplexer circuits in proxim... | 05/22/2007 |
| 7201947 | CPP and MTJ reader design with continuous exchange-coupled free layer As track widths of magnetic read heads grow very small, conventional longitudinal bias stabilization has been found to no longer be suitable since the strong magnetostatic coupling at the track edges also pins the magnetization of the free layer. This problem has be... | 04/10/2007 |
| 7202859 | Capacitive sensing pattern A capacitive sensor is disclosed. The capacitive sensor comprises a plurality of spaced-apart X traces disposed along an X axis and a plurality of spaced-apart Y traces disposed along a Y axis with each of the Y traces forming a single crossing with each of the X tr... | 04/10/2007 |
| 7196940 | Method and apparatus for a multiplexed address line driver A method and apparatus for multiplexing various voltage magnitudes onto the address line of a memory cell. An address line voltage generator applies complex analog voltage magnitudes to a memory cell address line during Power On Reset (POR) to insure proper memory c... | 03/27/2007 |
| 7197733 | Integrated circuit dynamic parameter management in response to dynamic energy evaluation A single integrated circuit (12). The integrated circuit comprises a first circuit (14x) having a data path, the first circuit consisting of a first number of logic gates for performing a plurality of logic functions. The integrated circuit ... | 03/27/2007 |
| 7193444 | High speed data bit latch circuit A latching circuit having a clock signal input and a data input, includes an inverting delay circuit having an input connected to DATA IN and having an output signal s1, a NAND circuit having a first input connected to signal s1, a second input connect... | 03/20/2007 |
| 7187610 | Flash/dynamic random access memory field programmable gate array A method for providing a circuit for selectively interconnecting N pairs of nodes in an integrated circuit device comprising: providing a memory array having a plurality of wordlines and a plurality of bitlines; providing a plurality of dynamic random access memory ... | 03/06/2007 |
| 7183796 | Configuration memory implementation for LUT-based reconfigurable logic architectures A reconfigurable processing unit (1) is described which comprises, data flow controlling elements (10), data manipulating elements (20), a configuration memory unit (30) comprising a plurality of memory cells (31a, . . . ) f... | 02/27/2007 |
| 7174351 | Method for deleting stored digital data from write-once memory device A digital storage system is coupled to a write-once memory array. File delete commands are implemented by over-writing a destructive digital pattern to at least a portion of the memory cells associated with the file to be deleted. One disclosed system alters the man... | 02/06/2007 |
| 7170316 | Programmable logic array latch A programmable logic array (PLA) latch is disclosed. The PLA latch includes a first logic array, a second logic array and only one output latch. The second logic array is coupled to the first logic array. The output latch is coupled to the second logic array. ... | 01/30/2007 |
| 7157314 | Vertically stacked field programmable nonvolatile memory and method of fabrication A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus ... | 01/02/2007 |
| 7148722 | PCI-compatible programmable logic devices A programmable logic integrated circuit device has several features which help it perform according to the PCI Special Interest Group's Peripheral Component Interface (“PCI”) signaling protocol. Some of the registers on the device are closely coupled for data in... | 12/12/2006 |
| 7131089 | Computer program for programming an integrated circuit speed capability indicator A computer programmed to specify a design of a circuit for indicating a potential speed capability of a data path in a predetermined circuit. The data path comprises a plurality of logic functions to be performed by a first number of logic gates. The computer specif... | 10/31/2006 |
| 7126369 | Transceiver providing high speed transmission signal using shared resources and reduced area A transceiver provides a high-speed transmission signal using shared resources and reduced area. A differential amplifier has its current source/sink connected to a supply terminal. A multiplexing circuit is configured to connect an input of the differential amplifi... | 10/24/2006 |
| 7116131 | High performance programmable logic devices utilizing dynamic circuitry A programmable logic device (PLD) includes dynamic lookup table (LUT) circuits, an interconnect structure implemented in either dynamic or static logic, and optional static logic circuits. Each dynamic LUT circuit has paired true and complement input terminals and p... | 10/03/2006 |
| 7109771 | Semiconductor integrated circuit with reduced leakage current A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores a... | 09/19/2006 |
| 7109978 | Object position detector with edge motion feature and gesture recognition A method of generating a signal comprising providing a capacitive touch sensor pad including a matrix of X and Y conductors, developing capacitance profiles in one of an X direction and a Y direction from the matrix of X and Y conductors, determining an occurrence o... | 09/19/2006 |
| 7111110 | Versatile RAM for programmable logic device Circuits and methods for providing versatile RAM for a programmable logic device are provided. These circuits and methods preferably allow signal lines that may be used to provide inputs for logic elements to be used instead for addressing memory blocks that form th... | 09/19/2006 |
| 7107566 | Programmable logic device design tools with gate leakage reduction capabilities Power consumption on programmable logic devices can be minimized by taking account of gate leakage effects. A logic design system may analyze a logic design to determine which signals are most often high and which signals are low. A logic designer may also provide i... | 09/12/2006 |
| 7100143 | Method and apparatus for pre-tabulating sub-networks Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the... | 08/29/2006 |
| 7098755 | High power, high linearity and low insertion loss single pole double throw transmitter/receiver switch A high performance single-pole-double-throw (SPDT) Transmitter/Receiver (T/R) FET switch utilizes a plurality of multi-gate FETs in series to realize low insertion loss, low harmonic distortion and high power handling capabilities. The SPDT switch consists of an ant... | 08/29/2006 |
| 7098689 | Disabling unused/inactive resources in programmable logic devices for static power reduction A method of operating a programmable logic device, including the steps of enabling resources of the programmable logic device being used in a circuit design implemented by the programmable logic device, and disabling unused or inactive resources of the programmable ... | 08/29/2006 |
| 7091519 | Semiconductor thin film, semiconductor device and manufacturing method thereof A semiconductor device includes a substrate having an insulating film on its surface, and ac active layer made of a semiconductive thin film on the substrate surface. The thin film contains a mono-domain region formed of multiple columnar and/or needle-like crystals... | 08/15/2006 |
| 7084666 | Programmable interconnect structures A programmable interconnect structure in an integrated circuit comprising: a plurality of wires; and a buffer comprising an input and an output, said buffer receiving a weak signal at the input and providing a buffered signal at the output; and a first programmable ... | 08/01/2006 |
| 7081772 | Optimizing logic in non-reprogrammable logic devices A method for reducing the amount of logic needed to perform logic operations in non-reprogrammable logic devices based on preexisting circuit designs is provided. The logic optimization method reduces die size and power consumption while increasing the performance o... | 07/25/2006 |
