In 1879, Auguste Bartholdi received design patent number 11,023 titled "Design for a Statue". It was for the Statue of Liberty.
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| Number | Title | Issue Date |
| 7304497 | Methods and apparatus for programmably powering down structured application-specific integrated circuits Methods and apparatus for programmably powering down a structured application-specific integrated circuit are provided. At least one of the programmable layers of the structured ASIC that frequently provides some programmability as between or among a small number of... | 12/04/2007 |
| 7081772 | Optimizing logic in non-reprogrammable logic devices A method for reducing the amount of logic needed to perform logic operations in non-reprogrammable logic devices based on preexisting circuit designs is provided. The logic optimization method reduces die size and power consumption while increasing the performance o... | 07/25/2006 |
| 6650141 | High speed interface for a programmable interconnect circuit A programmable semiconductor device comprising a plurality of I/O circuits arranged into blocks includes a routing structure for each block, wherein each routing structure may programmably route signals between its block's I/O circuits and the I/O circuit... | 11/18/2003 |
| 6359467 | Dynamic element matching using current-mode butterfly randomization The present invention is a technique for dynamic element matching used in digital-to-analog converters (DAC's). An analog-to-digital converter (ADC) converts an analog signal into a digital code. A current-mode randomizer randomizes the digital code based... | 03/19/2002 |
| 6285218 | Method and apparatus for implementing logic using mask-programmable dynamic logic gates A method and apparatus for implementing dynamic logic with programmable dynamic logic gates acts as a complement to programmable logic arrays (PLAs) used in high-speed microprocessor designs. A matrix of selectable cells provides powerful logic functions ... | 09/04/2001 |
| 5467027 | Programmable cell with a programmable component outside the signal path An electronic circuit comprises a programmable cell that comprises a cell input, an output, a programmable component, programming means for selectively changing a state of the component, and coupling means for providing a signal path from the cell input t... | 11/14/1995 |
| 5338982 | Programmable logic device A semiconductor integrated circuit capable of electrically writing functions according to this invention comprises a plurality of logical blocks capable of electrically writing functions and wire elements capable of programmably connecting the logical blo... | 08/16/1994 |
| 5302864 | Analog standard cell An analog standard cell includes a functional circuit portion and an interface circuit portion, the functional circuit portion being selected from a library of circuits having different circuit arrangements and an identical function, and the interface cir... | 04/12/1994 |
| 5132573 | Semiconductor gate array device compatible with ECL signals and/or TTL signals A semiconductor gate array device compatible with ECL and/or TTL, wherein the input buffer unit includes a TTL input stage, an ECL input stage and a common output stage, and the output buffer unit includes a common input stage, an ECL output stage and a T... | 07/21/1992 |
| 5128558 | High speed, low power consumption voltage switching circuit for logic arrays A memory device (10) includes switching circuitry 22 comprising sensing and control circuits (24 and 26) to predict the next state of the output of memory device (12) and to turn on and off current sources (20) responsive to said memory output to provide ... | 07/07/1992 |
| 5103120 | Level conversion circuitry for a semiconductor integrated circuit In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a b... | 04/07/1992 |
| 5086240 | Programmable integrated logic network having bipolar and MOS transistors Each programming point (11) of the programmable logic network (10) according to the invention is made with a field effect transistor (N1), the gate and drain of which are connected respectively to the input (Lx) and output (Ly) lines, and the source of wh... | 02/04/1992 |
| 5077493 | Wired logic circuit for use in gate array integrated circuit A gate array integrated circuit includes four internal logic circuits each composed of a current mode logic circuit and an emitter follower circuit having an input connected to an output of the current mode logic circuit. One wired logic circuit is formed... | 12/31/1991 |
| 5055716 | Basic cell for BiCMOS gate array An improved cell for use in a mask programmable gate array is disclosed herein. The preferred cell comprises two compute sections, each comprising two pairs of medium size P and N-channel transistors, two small N-channel transistors, and a single small P-... | 10/08/1991 |
| 5045726 | Low power programming circuit for user programmable digital logic array A programming circuit for an array of bipolar transistors which is selectable by row and column decoders to form a selected logic circuit, programming being effected by thermal links respectively connected to the respective transistors and which undergo a... | 09/03/1991 |
| 5001474 | Switching matrix for telecommunication exchanges A switch matrix for telecommunication including change-over switches which can be used for both analog and digital signal transmission. Each change-over switch includes a selector circuit, an input and an output stage. The output stage generally includes ... | 03/19/1991 |
| 4939391 | Programmable logic device with observability and preload circuitry for buried state registers A programmable array logic device including a programmable logic array, at least one register pair, a multiplexer coupled to the register pair so that they can share a common I/O pin, and an observability buffer for controlling the multiplexer. A dual clo... | 07/03/1990 |
| 4910508 | Matrix logic circuit network suitable for large-scale integration A matrix logic circuit network comprises a great number of interconnected logic gates. Input and output lines of the logic gates are arranged in the matrix array. By rearranging the input and output lines of the matrix in accordance with a sort algorithm,... | 03/20/1990 |
| 4879480 | Bicmos gate array In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a b... | 11/07/1989 |
| 4859874 | PLA driver with reconfigurable drive In accordance with the teachings of this invention, a novel PLA row driver circuit is provided which utilizes a minimum number of components, thereby minimizing integrated circuit surface area, and thus reducing cost, and minimizing stray capacitance, the... | 08/22/1989 |
| 4849933 | Bipolar programmable logic array A bipolar programmable logic array for producing a substantially constant current to a common sense line (16) includes a bandgap circuit portion (14) for generating a temperature-dependent reference voltage and a current source (IS) responsive to the temp... | 07/18/1989 |
| 4789797 | Temperature-compensated interface circuit between "OR-tied" connection of a PLA device and a TTL output buffer An interface circuit (110) for interfacing between an "OR-tied" connection (P) of a programmable logic array device (10) and a TTL output buffer (36) includes a first bandgap generator (40), a high level clamp circuit (30), a second bandgap generator circ... | 12/06/1988 |
| 4758994 | On chip voltage regulator for common collector matrix programmable memory array A programmable memory includes a voltage regulator (32) which is disposed between the supply voltage and the matrix supply line (10) for programmable memory cells. Each of the memory cells is comprised of a transistor (12) and a series fusible link (16). ... | 07/19/1988 |
| 4730130 | Writable array logic A bipolar writable array logic device is provided having an output representing a logical AND function and a logical OR function in response to a plurality of input signals. An AND matrix decode and an OR matrix decode are coupled to an input circuit for ... | 03/08/1988 |
| 4725745 | Bi-MOS PLA An integrated programmable logic array formed within a single silicon chip comprises a combination of a logical product gate array and a logical summation gate array. The logical product gate array is equipped with a plurality of MIS field-effect transist... | 02/16/1988 |
| 4689502 | Gate array LSI device using PNP input transistors to increase the switching speed of TTL buffers A gate array LSI device having inner gate circuits whose performance is not affected by the load condition and having a large fan-out number. The inner gate circuit comprises one or more PNP-type transistors, each of which receives an input signal at the ... | 08/25/1987 |
| 4682202 | Master slice IC device A master slice IC device comprising at least two kind of basic cells; that is, a first kind of basic cells each having one or more n-type MIS transistors and one or more p-type MIS transistors to form a CMIS logic circuit, and a second kind of basic cells... | 07/21/1987 |
| 4659947 | PLA with forward-conduction bipolar "and" array and I2 L "OR" array An integrated programmable logic array formed within a single silicon chip comprises a combination of an NAND or AND gate array and an NOR or OR gate array. The NAND or AND gate array includes a plurality of bipolar transistors which are driven to operate... | 04/21/1987 |
| 4645953 | Current source which saves power in programmable logic array circuitry A current source for powering programmable arrays which provides means of eliminating the current supplied to portions of the array which are unimportant to the boolean arithmetic equation which the programmable array is programmed to model. The circuit i... | 02/24/1987 |
| 4644191 | Programmable array logic with shared product terms A programmable logic circuit comprises a Programmable Array Logic (PAL) circuit in which individual product terms may be shared simultaneously by one or more of the circuit outputs. The product terms are selectively connected to the circuit outputs by pro... | 02/17/1987 |
| 4628217 | Fast scan/set testable latch using two levels of series gating with one current source An economical circuit of n transistors and m resistors (n=4, m=1 for Emitter Coupled Logic (ECL); n=3, m=0 for Current Mode Logic (CML)) interconnects to a fast differential feedback latch of r transistors and s resistors (r=12, s=9 for ECl; r=7, s=3 for ... | 12/09/1986 |
| 4534008 | Programmable logic array Given a programmable logic array, all product terms of the product matrix are applied to a prescribable potential by way of a first control signal so that the following sum matrix is no longer influenced by the input variables. Additional transfer element... | 08/06/1985 |
| 4525714 | Programmable logic array with test capability in the unprogrammed state A programmable circuit array comprises an input buffer adapted to receive a plurality of input signals for outputting equivalent input signals and inverted input signals. A programmable product array receives the equivalent input signals and the inverted ... | 06/25/1985 |
| 4413191 | Array word line driver system This invention provides a system for selectively driving one word line of a plurality of word lines in a memory array which includes a first highly capacitive common line connected to a plurality of driver circuits, each of which has connected to its outp... | 11/01/1983 |
| 4378508 | EFL Logic arrays A logic gate is formed as a full 3-EFL circuit including a full two-level ECL current switch tree and an EFL stage made up of input and output multiemitter transistors. By appropriate connections, the logic gate may be used for a variety of circuits inclu... | 03/29/1983 |
| 4228525 | Semiconductor integrated circuit device A semiconductor integrated circuit device has an array of memory cells formed by integrated injection logic. A desired number of dummy cells are provided at both ends of each line of the array, so that a write current, which flows when the memory cell nea... | 10/14/1980 |
| 4215282 | Temperature compensated sense amplifier for PROMs and the like A sense amplifier and sensing scheme for sensing the normal or blown condition of fuses in a programmable read only memory (PROM) or similar device. A sensing circuit is provided with a threshold level separating high and low input levels indicative of th... | 07/29/1980 |
| 4192016 | CMOS-bipolar EAROM A memory array having NPN emitter followers with B VEB >20 volts and high threshold electrically alterable devices in each cell, CMOS row and column address buffer drivers and CMOS outputs buffers. The row address buffer includes an emitter fol... | 03/04/1980 |
| 4025909 | Simplified dynamic associative cell This specification describes an associative memory cell capable of performing logic functions. The cell comprises two transistors with their collectors connected to an output line; with their emitters either left floating or connected to an input line car... | 05/24/1977 |
| 3941940 | Transient suppressor A diode OR gate permits trigger circuits of an array of SCR's to share the same integrating capacitor for suppression of short-lived transients, which might otherwise cause false triggering of the SCR's. The SCR's are switching and latching elements in a ... | 03/02/1976 |