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| Number | Title | Issue Date |
| 8159266 | Metal configurable integrated circuits A metal programmable semiconductor device is disclosed. The semiconductor device, comprises: a metal programmable logic circuit; and a plurality of fixed interconnect geometries including metal and via structures; and a plurality of selectable interconnect geometrie... | 04/17/2012 |
| 8161435 | Reset mechanism conversion Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described. These may operate to convert synchronous state holding blocks that include reset signals to corresponding a... | 04/17/2012 |
| 8154319 | Three-dimensional architecture for integration of CMOS circuits and nano-material in hybrid digital circuits A hybrid CMOL stack enables more efficient design of CMOS logical circuits. The hybrid CMOL structure includes a first substrate having a CMOS device layer on the substrate, a first interconnect layer with interface pins over the CMOS device layer of the first subst... | 04/10/2012 |
| 8151238 | Semiconductor integrated circuit and design method thereof In a layout process of a semiconductor integrated circuit, a power supply is initially formed in an arrangement in which the current threshold value is not exceeded. In a case where the excess over the current threshold value occurs after the power supply is formed,... | 04/03/2012 |
| 8143914 | Semiconductor integrated circuit A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of swi... | 03/27/2012 |
| 8138790 | Latency measurements for wireless communications In one embodiment, a programmable logic device (PLD) includes a programmable fabric and hard logic coupled to the programmable fabric. The hard logic includes a timing measurement circuit adapted to measure latency of a data path between first and second points in t... | 03/20/2012 |
| 8125243 | Integrity checking of configurable data of programmable device Methods and a system for continuous integrity checking of configuration data of programmable device are disclosed. In one embodiment, a method includes performing a redundancy check (RC) of configuration data loaded to configuration registers to produce a master RC ... | 02/28/2012 |
| 8120382 | Programmable integrated circuit with mirrored interconnect structure A programmable integrated circuit (IC) with mirrored interconnect structure. The IC includes a plurality of arrangements, which are horizontally arranged. Each arrangement includes a first logic column, an interconnect column, and a second logic column. Each interco... | 02/21/2012 |
| 8111086 | Methods and systems for selective implementation of progressive display techniques The present disclosure relates to systems and methods for selective implementation of progressive display techniques based on a number of frames displayed in a window. A first hooking component identifies for a window displaying first application data on a local com... | 02/07/2012 |
| 8106682 | Permutable switching network with enhanced interconnectivity for multicasting signals In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuit... | 01/31/2012 |
| 8098082 | Multiple data rate interface architecture Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one p... | 01/17/2012 |
| 8098081 | Optimization of interconnection networks A method is implemented for generating a non-blocking routing network design from a crossbar switch-based network design. The non-blocking routing network design includes connections to logic blocks of a programmable integrated circuit. A programmed processor is use... | 01/17/2012 |
| 8072240 | Die apparatus having configurable input/output and control method thereof A metal configurable I/O structure for an integrated circuit is disclosed. The metal configurable I/O structure may be configured for one of any of a plurality of I/O specifications. Preferably a common voltage reference and a common current reference is generated f... | 12/06/2011 |
| 8063661 | Semiconductor device having circuit blocks with mutually the same circuit configuration To include a plurality of circuit blocks each including a plurality of nonvolatile memory elements arranged in the X direction, a plurality of comparing circuits that are respectively allocated to the nonvolatile memory elements, and a determining circuit that is co... | 11/22/2011 |
| 8049531 | General purpose input/output system and method A system for general purpose input-output (IO), including a first pad; an IO buffer comprising the first pad; and an IO datapath logic block operatively connected to the IO buffer, where the IO datapath logic block and the IO buffer are associated with a general pur... | 11/01/2011 |
| 8044682 | FPGA having low power, fast carry chain An in-FPGA carry chain is provided that does not exhibit significant leakage current. In particular, parts of the carry chain can be switched on/off when desired. In this manner, carry chain parts can have their leakage currents substantially disabled when they are ... | 10/25/2011 |
| 8024690 | Method, system and computer program product for determining routing of data paths in interconnect circuitry providing a narrow interface for connection to a first device and a wide interface for connection to a distributed plurality of further devices A system, method and computer program product are provided for determining routing of data paths in interconnect circuitry for an integrated circuit. The method includes the steps of defining a plurality of cells to be provided along the wide interface of the circui... | 09/20/2011 |
| 8018249 | Logic chip, logic system and method for designing a logic chip A logic chip has a plurality of individually addressable resource blocks each of the resource blocks having logic circuitry, and a communication bar extending across a plurality of the individually addressable resource blocks. The communication bar has a plurality o... | 09/13/2011 |
| 7999570 | Enhanced permutable switching network with multicasting signals for interconnection fabric In one embodiment, an integrated circuit has an L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors and (L+2) levels of conductors for L at least equal to one. An (i−1)-th level of conductors comprising Ii−1 num... | 08/16/2011 |
| 7994818 | Programmable interconnect network for logic array The present invention provides an integrated circuit, comprising an array of components and programmable interconnect network for the array of components, said programmable interconnect network comprising a plurality of switch boxes being connected in a tree-based h... | 08/09/2011 |
| 7986163 | Scalable non-blocking switching network for programmable logic A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect re... | 07/26/2011 |
| 7984415 | Merging of equivalent logic blocks in a circuit design Approaches for merging replicate logic blocks of a circuit design. Groups of replicate logic blocks in a placed circuit design are determined. For the replicate logic blocks in each group, a determination is made whether or not to merge replicate logic blocks in a s... | 07/19/2011 |
| 7982497 | Multiplexer-based interconnection network The logical functionality of a non-blocking multiplexer-based network is equivalent to a crossbar network with an ingress stage, a middle stage and an egress stage. Crossbar rows of the crossbar network include both outbound and inbound internal connections between ... | 07/19/2011 |
| 7973559 | Method for fabrication of a semiconductor element and structure thereof Re-programmable antifuses and structures utilizing re-programmable antifuses are presented. Such structures include a configurable interconnect circuit having at least one re-programmable antifuse, wherein the at least one re-programmable antifuse is configured to b... | 07/05/2011 |
| 7965102 | Formation of columnar application specific circuitry using a columnar programmable device A columnar programmable device (PD) design converted to a columnar application specific integrated circuit-like (ASIC-like) design is described. A user design is instantiated in a PD having a columnar architecture associated with the columnar PD design. The columnar... | 06/21/2011 |
| 7961004 | FPGA having a direct routing structure A FPGA comprising, a direct interconnect structure for providing selective data routing without stressing the general-purpose routing resources and enabling high rate of data exchange within the FPGA. At least two IP cores are connected to each other through said di... | 06/14/2011 |
| 7949971 | Method and apparatus for on-the-fly minimum power state transition The invention includes a design structure embodied in a computer readable medium for performing a method for inserting a scan chain into a VLSI circuit design. The scan chain structure, or structures, are included in the design structure for the VLSI circuit design.... | 05/24/2011 |
| 7936184 | Apparatus and methods for adjusting performance of programmable logic devices A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and ... | 05/03/2011 |
| 7930670 | Using selectable in-line inverters to reduce the number of inverters in a semiconductor design Logic array devices having complex macro-cell architecture and methods facilitating use of same. A semiconductor device comprising an array of logic cells and programmable metal includes gate structures that are pre-wired, where, inputs and/or outputs are available ... | 04/19/2011 |
| 7928764 | Programmable interconnect network for logic array A programmable interconnect network for an array of logic cells. Said interconnect network has a plurality of switch boxes being connected in a tree structure and providing connections to its logic cells, switch boxes located at the lowest level of the tree structur... | 04/19/2011 |
| 7924052 | Field programmable gate array architecture having Clos network-based input interconnect A cluster internal routing network for use in a programmable logic device with a cluster-based architecture employs a Clos network-based routing architecture. The routing architecture is a multi-stage blocking architecture, where the number of inputs to the first st... | 04/12/2011 |
| 7924053 | Clustered field programmable gate array architecture A logic cluster for a field programmable gate array integrated circuit device is disclosed. The cluster comprises a plurality of functional blocks and three levels of routing multiplexers. External signals enter the logic cluster primarily at the third level multipl... | 04/12/2011 |
| 7924054 | Latency measurements for wireless communications A programmable logic device (PLD), is provided that includes: a plurality of SERDES channels; a programmable logic fabric configured to implement an interface for a standardized cellular base station system; wherein the interface receives data words from the SERDES ... | 04/12/2011 |
| 7919979 | Field programmable gate array including a non-volatile user memory and method for programming An integrated circuit includes a programmable logic unit and an on-chip non-volatile memory. A JTAG port, TAP controller circuit, and program/erase control circuitry provide user access to the non-volatile memory for storage of user data. The non-volatile memory may... | 04/05/2011 |
| 7919980 | Configurable circuit and configuration method A configurable circuit of the present invention includes a plurality of logic blocks (4), and a programmable bus which can program connections of plurality of logic blocks (4). The programmable bus includes a plurality of wires (11—... | 04/05/2011 |
| 7915918 | Method and apparatus for universal program controlled bus architecture An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells compr... | 03/29/2011 |
| 7911229 | Programmable signal routing systems having low static leakage Parasitic static leakage current through input terminals of bus-accessing multiplexers is minimized by automatically forcing as many as practical of the bus lines into a high impedance state where all drivers of the lines are in a high impedance output state. Thus p... | 03/22/2011 |
| 7911230 | Omnibus logic element for packing or fracturing Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table. ... | 03/22/2011 |
| 7902865 | Compression and decompression of configuration data using repeated data frames Various techniques are provided to compress and decompress configuration data for use with programmable logic devices (PLDs). In one example, a method includes embedding a first data frame comprising a data set from an uncompressed bitstream into a compressed bitstr... | 03/08/2011 |
| 7902868 | Field programmable gate arrays using resistivity sensitive memories Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non... | 03/08/2011 |
