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| Number | Title | Issue Date |
| 8115512 | Method and apparatus for dynamically aligning high-speed signals in an integrated circuit A method and apparatus for dynamically aligning high-speed signals in an integrated circuit are disclosed. For example, an integrated circuit according to one embodiment includes a logic fabric and at least one input/output interface coupled to the logic fabric. The... | 02/14/2012 |
| 8089300 | Users registers implemented with routing circuits in a configurable IC Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing ... | 01/03/2012 |
| 8072239 | Element controller for a resilient integrated circuit architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element contr... | 12/06/2011 |
| 8063660 | Method and apparatus for configurable address translation A technique is applicable to a device having programmable circuitry that includes a first interface having a plurality of first address terminals, a second interface having a plurality of second address terminals, and a configurable interconnect structure coupled be... | 11/22/2011 |
| 8058900 | Method and apparatus for clocking Aspects of the disclosure provide a clock gate circuit for generating a clock signal. The clock gate circuit can include a multiplexer configured to receive a first logic signal at a first data input, a second logic signal at a second data input, and a reference clo... | 11/15/2011 |
| 8040154 | Software programmable logic using spin transfer torque magnetoresistive devices Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The... | 10/18/2011 |
| 8015530 | Method of enabling the generation of reset signals in an integrated circuit A method of enabling the generation of reset signals in an integrated circuit is disclosed. The method comprises receiving information related to reset ports for a plurality of intellectual property cores in a design tool; providing an intellectual property core com... | 09/06/2011 |
| 8004309 | Programmable logic device structure using third dimensional memory A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configu... | 08/23/2011 |
| 7992118 | Semiconductor integrated circuit and design method for semiconductor integrated circuit The semiconductor integrated circuit of the invention includes: two first power supply lines placed in parallel in a same interconnect layer; a second power supply line placed between the two first power supply lines in the same interconnect layer; an actual operati... | 08/02/2011 |
| 7944238 | (N+1) input flip-flop packing with logic in FPGA architectures A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multip... | 05/17/2011 |
| 7940082 | Circuits and method for bypassing a static configuration in a programmable logic device to implement a dynamic multiplexer Circuit for selectively using static or dynamic select signals inside an integrated circuit, including a first transistor connecting a static select signal to a dynamic route select output line when a dynamic select CRAM signal is at a first logical level, and a sec... | 05/10/2011 |
| 7932745 | Inverting flip-flop for use in field programmable gate arrays A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and... | 04/26/2011 |
| 7915917 | Integrated circuit with improved logic cells The present invention provides integrated circuits with improved logic cells. In one embodiment, an integrated circuit having a plurality of logic cells (LC) is provided, each LC comprising: a lookup table having a LUT output terminal; and, a first multiplexer; wher... | 03/29/2011 |
| 7911228 | Integrated circuit with improved logic cells The present invention provides integrated circuits with improved logic cells. In one embodiment, an integrated circuit having a plurality of logic cells (LC) is provided, each LC comprising: a lookup table having a LUT output terminal; and, a first multiplexer; wher... | 03/22/2011 |
| 7863931 | Flexible delay cell architecture A flexible delay cell architecture and related methods are provided that may be used, for example, with input/output (I/O) blocks of a programmable logic device (PLD). In one implementation, a PLD includes a delay cell comprising a plurality of delay elements. The d... | 01/04/2011 |
| 7859303 | Nonvolatile programmable logic circuit A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPG... | 12/28/2010 |
| 7830171 | Method and apparatus for initializing an integrated circuit Method and apparatus for initializing an integrated circuit are described. A static memory includes an array of memory cells having control lines coupled to a column select component and data lines coupled to a register component. The static memory is formed in one ... | 11/09/2010 |
| 7816946 | Inverting flip-flop for use in field programmable gate arrays A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and... | 10/19/2010 |
| 7750672 | Element controller for a resilient integrated circuit architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element contr... | 07/06/2010 |
| 7733124 | Method and apparatus for PLD having shared storage elements A programmable logic device (PLD) includes a core region having a plurality of logical array blocks (LABs). Each one of the plurality of logical array blocks include a plurality of logic elements capable of communicating with each other through interconnections defi... | 06/08/2010 |
| 7728622 | Software programmable logic using spin transfer torque magnetoresistive random access memory Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The... | 06/01/2010 |
| 7724030 | Method and apparatus for providing a feedback path for an output signal In one embodiment, an integrated device is disclosed. For example, in one embodiment of the present invention, a device comprises a core module for providing one or more output signals. The device comprises an output logic module for receiving the one or more output... | 05/25/2010 |
| 7719311 | Integrated circuit with improved logic cells The present invention provides integrated circuits with improved logic cells. In one embodiment, an integrated circuit having a plurality of logic cells (LC) is provided, each LC comprising: a lookup table having a LUT output terminal; and, a first multiplexer; wher... | 05/18/2010 |
| 7714609 | Method and apparatus to power down unused configuration random access memory cells A method for reducing power consumption for a programmable logic device (PLD) is provided. In the method, configuration cells associated with used logic portions of the PLD are powered. A programmable power signal preventing source to drain leakage is provided to an... | 05/11/2010 |
| 7701250 | (N+1) input flip-flop packing with logic in FPGA architectures A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multip... | 04/20/2010 |
| 7696783 | Logic modules for semiconductor integrated circuits A logic module (400) that is capable of implementing data-path and random logic (command Z in block 42) uses control logic for selectively coupling one or more of the input terminals (10, 12, 14, 16, 18, 40) to the at least one output terminal (... | 04/13/2010 |
| 7679401 | User registers implemented with routing circuits in a configurable IC Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing ... | 03/16/2010 |
| 7656192 | Three dimensional integrated circuits A programmable integrated circuit (IC), comprising: a programmable logic circuit configured by a first control signal coupled to a gate electrode of a transistor in the logic circuit; and a first plurality of read only memory (ROM) elements capable of coupling to th... | 02/02/2010 |
| 7656193 | Programmable logic device and method of testing In one embodiment of the invention, a programmable logic device includes a plurality of programmable resources; non-volatile configuration memory adapted to store configuration data for configuring the plurality of programmable resources; a register adapted to load ... | 02/02/2010 |
| 7656191 | Distributed memory in field-programmable gate array integrated circuit devices Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data pa... | 02/02/2010 |
| 7652501 | Programmable logic device structure using third dimensional memory A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configu... | 01/26/2010 |
| 7635988 | Multi-port thin-film memory devices In a first aspect, a semiconductor storage device, comprising: a metal line coupled to a gate of an access transistor, wherein the gate material is deposited substantially above the metal line. In a second aspect, a semiconductor storage device, comprising: a first ... | 12/22/2009 |
| 7598769 | Apparatus and method for a programmable logic device having improved look up tables A programmable logic device including a plurality of logic elements organized in an array. Each of the logic elements includes an N-stage Look Up Table structure having 2N configuration bit inputs and a Look Up Table output. The first stage of the Look Up... | 10/06/2009 |
| 7589556 | Dynamic control of memory interface timing Circuits, methods, and apparatus for the dynamic control of calibration data that adjusts the timing of input and output signals on an integrated circuit. This dynamic control allows input and output circuits to self-calibrate by compensating for temperature and vol... | 09/15/2009 |
| 7576562 | Diagnosable structured logic array A diagnosable structured logic array and associated process is provided. A base cell structure is provided comprising a logic unit comprising a plurality of input nodes, a plurality of selection nodes, and an output node, a plurality of switches coupled to the selec... | 08/18/2009 |
| 7573295 | Hard macro-to-user logic interface A hard macro-to-user logic interface of an integrated circuit is described. The integrated circuit includes a core as an application specific circuit block with a transaction interface of a first bit width and includes programmable logic capable of being programmed ... | 08/11/2009 |
| 7548091 | Method and apparatus to power down unused configuration random access memory cells A method for reducing power consumption for a programmable logic device (PLD) is provided. In the method, configuration cells associated with used logic portions of the PLD are powered. A programmable power signal preventing source to drain leakage is provided to an... | 06/16/2009 |
| 7538576 | Non-volatile look-up table for an FPGA A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. T... | 05/26/2009 |
| 7532032 | Configurable circuits, IC's, and systems Some embodiments of the invention provide configurable integrated circuit (IC) that has a first interface rate for exchanging signals with a circuit outside of the configurable IC. The configurable IC has an array of configurable circuits. The array includes several... | 05/12/2009 |
| 7525343 | Method and apparatus for accessing internal registers of hardware blocks in a programmable logic device A method and apparatus for accessing internal registers of hardware blocks in a programmable logic device (PLD) are described. An aspect of the invention relates to a method of accessing at least one internal register of a hardware block in a PLD. The PLD is activel... | 04/28/2009 |
