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| Number | Title | Issue Date |
| 8191025 | Redundancy structures and methods in a programmable logic device An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs fo... | 05/29/2012 |
| 8188763 | Nonvolatile nanotube programmable logic devices and a nonvolatile nanotube field programmable gate array using same Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performa... | 05/29/2012 |
| 8183881 | Configuration memory as buffer memory for an integrated circuit Method and apparatus for using configuration memory for buffer memory is described. Drivers associated with a portion of the configuration memory are rendered incapable of creating a contentious state irrespective of information stored the portion of configuration m... | 05/22/2012 |
| 8183882 | Reconfigurable IC that has sections running at different reconfiguration rates Some embodiments provide a reconfigurable IC that includes several sections. Each section includes several configurable circuits, each of which configurably performs a set of operations. Each section stores multiple configuration data sets for each configurable circ... | 05/22/2012 |
| 8185861 | Variable sized soft memory macros in structured cell arrays, and related methods The logic cells (HLEs) of a structured application-specific integrated circuit (structured ASIC) can be used to provide memory blocks of various sizes. Any one or more of several techniques may be employed to facilitate doing this for various user designs that may h... | 05/22/2012 |
| 8179159 | Configuration interface to stacked FPGA A method of configuring a stacked integrated circuit (“IC”) having a first IC die with configurable logic and a second IC die electrically coupled to the first IC die through an array of inter-chip contacts includes: providing a frame having frame data and a fra... | 05/15/2012 |
| 8174287 | Processor programmable PLD device A device including a PLD with at least one interface logic block connection for passing data between (i) a bus arranged for receiving data from an external processor and (ii) at least one I/O register connected with a JTAG interface of the PLD, wherein said interfac... | 05/08/2012 |
| 8159265 | Memory for metal configurable integrated circuits Memory for a semiconductor device is disclosed. The memory array comprises: a memory cell replicated in rows and columns to form an array; and a plurality of first horizontal decode signals, each horizontal signal common to all the memory cells in a said row; and a ... | 04/17/2012 |
| 8159263 | Programmable integrated circuit with voltage domains A programmable integrated circuit having a plurality of individually controlled voltage domains. Each voltage domain includes logic circuitry powered by a respective power network. The voltage magnitude of each power network is independently selectable. Each of a pl... | 04/17/2012 |
| 8159264 | Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements Some embodiments provide a circuit for accessing stored data in a configurable IC that includes several configurable circuits. The IC also includes several storage circuits. Each storage circuit has (1) several storage elements for storing data for the configurable ... | 04/17/2012 |
| 8143913 | Semiconductor integrated circuit, semiconductor integrated circuit control method, and terminal system A semiconductor integrated circuit judges whether a power unit is performing a discharge operation or a charge operation. To reduce clock skew between a plurality of logic blocks in the semiconductor integrated circuit, when the power unit is performing the charge o... | 03/27/2012 |
| 8138788 | Reconfigurable device There is provided a reconfigurable device that includes a plurality of processing blocks (13), wherein operation logic of each processing block is changeable, and a routing matrix (15) for configuring paths that connect the plurality of the processing ... | 03/20/2012 |
| 8138789 | Configuration context switcher with a clocked storage element Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. Th... | 03/20/2012 |
| 8136071 | Three dimensional integrated circuits and methods of fabrication The invention relates to multi-planar logic components in a three-dimensional (3D) integrated circuit (IC) apparatus configuration. A multi-planar integrated circuit connected by through silicon vias is configured to connect microprocessor, FPGA and memory component... | 03/13/2012 |
| 8115510 | Configuration network for an IC Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits grouped in several tiles. The configurable IC also includes a configuration network for loading configuration data into the IC, where the con... | 02/14/2012 |
| 8106680 | Programmable logic device with a self-power down mechanism Apparatuses for reducing power consumption in a programmable logic device (PLD) with a self power down mechanism are disclosed. Methods and a machine readable medium for restoring a prior known state are provided. The prior known state is stored in a memory module b... | 01/31/2012 |
| 8106679 | Data processing system The present invention provides an architecture code 20 including object circuit information 23 for mapping an object circuit that is at least part of a circuit for executing an application onto part of a logic circuit where circuits can be dynamically ... | 01/31/2012 |
| 8106681 | Semiconductor device, and programming method and programming system therefor In a method of programming a differential programming semiconductor device, first identification data corresponding to first program data is outputted from an ID register of a program circuit in the device to a host. The first program data is programmed in a plurali... | 01/31/2012 |
| 8102188 | Method of and system for implementing a circuit in a device having programmable logic A method of implementing a circuit in a device having programmable resources and a predetermined amount of available internal memory is disclosed. The method comprises configuring the programmable resources of the device with a circuit design; storing a first page o... | 01/24/2012 |
| 8102187 | Localized calibration of programmable digital logic cells An integrated circuit (IC) includes self-calibrating programmable digital logic circuitry. The IC includes at least one programmable digital logic cell, wherein the first programmable digital logic cell provides (i) a plurality of different accessible circuit config... | 01/24/2012 |
| 8098080 | Semiconductor programmable device An ePLX unit includes a logic unit having an SRAM and a MUX, and a switch unit having an SRAM and a TG for establishing wiring connection in the logic unit. When a composite module is set in the first mode, an Add/Flag control unit uses the SRAMs as a data field and... | 01/17/2012 |
| 8093922 | Configurable IC having a routing fabric with storage elements Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabr... | 01/10/2012 |
| 8089299 | Integrated circuit with through-die via interface for die stacking and cross-track routing An integrated circuit die is described that includes an array of tiles arranged in columns. The integrated circuit die includes interface tiles having at least one row of through die vias. The integrated circuit die includes metal layers that include horizontal wiri... | 01/03/2012 |
| 8085064 | Logic module including versatile adder for FPGA A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by ... | 12/27/2011 |
| 8076955 | Configurable logic device The configurable logic device comprises a plurality of configurable logic cells (2). A configurable logic cell comprises a plurality of multi-bit registers (20a, 20b, 20c, 20d). At least one is accessibl... | 12/13/2011 |
| 8072236 | Download sequencing techniques for circuit configuration data Methods, systems, and devices are described for the implementation of a novel architecture to support download sequencing techniques for circuit configuration data. Sets of configuration data from nonvolatile memory may be sequentially transferred to volatile memory... | 12/06/2011 |
| 8067960 | Runtime loading of configuration data in a configurable IC Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular opera... | 11/29/2011 |
| 8063659 | Low depth programmable priority encoders An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The sec... | 11/22/2011 |
| 8058896 | Flexible parallel/serial reconfigurable array configuration scheme A programming interface device for a programmable logic circuit comprises a series of parallel logic block chains each having first and second connection means, the first and second connection means being disposed at opposite ends of each chain. The programming inte... | 11/15/2011 |
| 8058898 | Compression and decompression of configuration data using repeated data frames In one embodiment, a method of converting an uncompressed bitstream into a compressed bitstream for a programmable logic device (PLD) is disclosed. The method includes embedding a first data frame from the uncompressed bitstream into the compressed bitstream, wherei... | 11/15/2011 |
| 8058897 | Configuration of a multi-die integrated circuit A method of configuring an integrated circuit (IC) can include receiving configuration data within a master die of the IC. The IC can include the master die and a slave die. A master segment and a slave segment of the configuration data can be determined. The slave ... | 11/15/2011 |
| 8044681 | Apparatus and method for channel-specific configuration in a readout ASIC An application-specific integrated circuit (ASIC) comprising a plurality of channels, each channel having circuitry for time and energy discrimination, a plurality of programmable registers, each programmable register configured to output at least one configuration ... | 10/25/2011 |
| 8040151 | Programmable logic device with programmable wakeup pins A programmable logic device (PLD) adapted to enter a low-power or sleep mode with programmable wakeup pins in a wakeup group of pins is disclosed. Wake on a single pin change, wake on vector, and wake on a single pin transition are supported. The approach is to sele... | 10/18/2011 |
| 8040152 | Separate configuration of I/O cells and logic core in a programmable logic device A programmable logic device (PLD) is provided that includes: a plurality of programmable logic blocks, the plurality of programmable logic blocks being associated with a first configuration data shift register operable to shift in configuration data for the pluralit... | 10/18/2011 |
| 8035414 | Asynchronous logic automata A family of reconfigurable, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements p... | 10/11/2011 |
| 8032853 | Configuration information writing apparatus, configuration information writing method and computer program product A configuration information writing apparatus for writing configuration information defining a logical configuration of a logic circuit device into the logic circuit device to change the logical configuration thereof, the apparatus comprising: a difference extractin... | 10/04/2011 |
| 8030962 | Configuration random access memory Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the in... | 10/04/2011 |
| 8022724 | Method and integrated circuit for secure reconfiguration of programmable logic Approaches for secure configuration of a programmable logic integrated circuit (IC). In one approach, a method includes programming configuration memory of the programmable logic IC with a first configuration bitstream. At least a portion of a second configuration b... | 09/20/2011 |
| 8018248 | Adjustable interface buffer circuit between a programmable logic device and a dedicated device An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedde... | 09/13/2011 |
| 8013629 | Reconfigurable logic automata A family of reconfigurable asynchronous logic elements that interact with their nearest neighbors permits reconfigurable implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information... | 09/06/2011 |
