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| Number | Title | Issue Date |
| RE43378 | Mapping of programmable logic devices A method for mapping an electronic digital circuit to a Look Up table (LUT) based Programmable Logic Deviceoperates by selecting an unmapped or partially mapped LUT, and identifying a group of circuit elements for mapping on the selected LUT based on the available c... | 05/08/2012 |
| 8138787 | Apparatus and method for input/output module that optimizes frequency performance in a circuit A circuit can include a module having signal pads that are configurable to route signals between the circuit and at least one external device. The module can also have unused pads that are interleaved between the signal pads. A circuit can include a module having si... | 03/20/2012 |
| 8099704 | Performance improvements in an integrated circuit by selectively applying forward bias voltages Methods and systems to improve performance in an Integrated Circuit (IC) are presented. The method includes performing a timing analysis for a circuit design of an IC. The modules in the circuit design use a standard voltage bias by default. In one embodiment, the t... | 01/17/2012 |
| 8095902 | Design structure for couple noise characterization using a single oscillator A design structure for a computer-aided design system for generating a functional design model of an integrated circuit design (having nets comprising wires) determines critical parameters for coupling noise between the wires of the nets and acceptable limits for th... | 01/10/2012 |
| 8085063 | Power regulator circuitry for programmable logic device memory elements Power regulator circuitry for programmable memory elements on programmable logic device integrated circuits is provided. The programmable memory elements may each include a storage element formed from cross-coupled inverters and an address transistor. Address driver... | 12/27/2011 |
| 8067959 | Programmable delay line compensated for process, voltage, and temperature A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-d... | 11/29/2011 |
| 8037444 | Programmable control of mask-programmable integrated circuit devices An integrated circuit device such as a structured ASIC includes a mask-programmable portion and a post-fabrication-programmable portion. The mask-programmable portion includes circuitry that is able to read information from the post-fabrication-programmable portion ... | 10/11/2011 |
| 7994815 | Cross-point latch and method of operating the same Provided is a cross-point latch and a method of operating the cross-point latch. The cross-point latch includes a signal line, two control lines crossing the signal line, and unipolar switches disposed at crossing points between the signal line and the control lines... | 08/09/2011 |
| 7952386 | Data input/output multiplexer of semiconductor device There is provided an input/output multiplexer capable of reducing a layout area in designing a device by disposing first and second multiplexers at either side of a specific data input/output (I/O) pad. An apparatus for multiplexing data inputted or outputted to a g... | 05/31/2011 |
| 7911227 | Programmable logic block of FPGA using phase-change memory device Provided is a programmable logic block of a field-programmable gate array (FPGA). The programmable logic block includes a pull-up access transistor connected to a power source, an up-phase-change memory device connected to the pull-up access transistor, a down-phase... | 03/22/2011 |
| 7911226 | Power-up and power-down circuit for system-on-a-chip integrated circuit A power-up and power-down circuit for an integrated circuit includes a voltage regulator set for a first voltage. A first I/O pad is coupled internally to an input to the voltage regulator and to first internal circuits. The second voltage is externally coupled to t... | 03/22/2011 |
| 7886261 | Programmable logic device adapted to enter a low-power mode A programmable logic integrated circuit device adapted to enter a low-power mode is described. The integrated circuit device includes a programmable logic block, a first low-power mode control circuit programmed into a portion of the programmable logic block, a seco... | 02/08/2011 |
| 7859301 | Power regulator circuitry for programmable logic device memory elements Power regulator circuitry for programmable memory elements on programmable logic device integrated circuits is provided. The programmable memory elements may each include a storage element formed from cross-coupled inverters and an address transistor. Address driver... | 12/28/2010 |
| 7843214 | Semiconductor integrated circuit device having standard cell including resistance element A standard cell includes an input terminal, an output terminal, first and second inverters coupled in series between the input and output terminals, the first inverter including a first transistor of a first conductivity type and a second transistor of a second cond... | 11/30/2010 |
| 7830170 | Logic gate A logic gate comprises a first switch, a second switch, a data network and a keeping circuitry. The first switch is adapted to connect a logic node to a first potential responsive to a transition of an enabling signal. The second switch is adapted to connect the log... | 11/09/2010 |
| 7816943 | Programmable cycle state machine interface A programmable cycle state machine interface to a microcontroller comprising a programmable cycle state machine, a first and second data bus, a first and second control output, and a control input for programming the cycle of the state machine. The programmable natu... | 10/19/2010 |
| 7701246 | Programmable delay line compensated for process, voltage, and temperature A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-d... | 04/20/2010 |
| 7612581 | Apparatus for dynamic deployment of pin functions on a chip An apparatus for dynamic deployment of pin functions on a chip is disclosed in the present invention. The apparatus comprises: an input pin receiving unit, capable of integrating a plurality of pins and selecting pin functions according to a program; an output pin c... | 11/03/2009 |
| 7602212 | Flexible high-speed serial interface architectures for programmable integrated circuit devices An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes high-speed serial data signal interface channels, some of which include more circuitry that is dedicated to performing ... | 10/13/2009 |
| 7598767 | Multi-standard data communication interface circuitry for programmable logic devices A programmable logic device includes a hard IP portion, which includes circuitry that is dedicated to receiving a high-speed serial data signal and performing certain basic functions related to byte alignment on that data signal, and a more general-purpose programma... | 10/06/2009 |
| 7592832 | Adjustable transistor body bias circuitry An integrated circuit is provided that contain n-channel and p-channel metal-oxide-semiconductor transistors having body terminals. Adjustable transistor body bias circuitry is provided on the integrated circuit that provides body bias voltages to the body terminals... | 09/22/2009 |
| 7541832 | Low power, race free programmable logic arrays The present invention provides a PLA architecture where the AND plane is implemented with NAND logic. The OR plane may be implemented with various logic, but in one embodiment, the OR plane is implemented with NOR logic. The AND plane may have multiple sequential st... | 06/02/2009 |
| 7525340 | Programmable logic device architecture for accommodating specialized circuitry A programmable logic device (PLD) having one or more programmable logic regions and one or more conventional input/output regions additionally has one or more peripheral areas including specialized circuitry. The peripheral specialized regions, which are not connect... | 04/28/2009 |
| 7492183 | Programmable system on a chip for power-supply voltage and current monitoring and control A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip... | 02/17/2009 |
| 7492182 | Non-volatile look-up table for an FPGA A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. T... | 02/17/2009 |
| 7444456 | SRAM bus architecture and interconnect to an FPGA An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connect... | 10/28/2008 |
| 7444276 | Hardware acceleration system for logic simulation using shift register as local cache A logic simulation processor stores in a shift register intermediate values generated during the logic simulation. The simulation processor includes multiple processor units and an interconnect system that communicatively couples the processor units to each other. E... | 10/28/2008 |
| 7439774 | Multiplexing circuit for decreasing output delay time of output signal Disclosed herein is a multiplexing circuit for decreasing the output delay time of an output signal. The multiplexing circuit includes multiplexing units and a multiplexing output unit. Each multiplexing unit is initialized in response to an initialization signal, a... | 10/21/2008 |
| 7436208 | Carry circuit with power-save mode A carry circuit having a power-save mode and a method for reducing power consumption of an integrated circuit are described. A power-save input is selected for control select signaling. A voltage level input is selected as an initial carry input. The initial carry i... | 10/14/2008 |
| 7436218 | Magnetic AND/NOR circuit A magnetic AND/NOR circuit has a first, a second, a third, and a fourth magnetic transistor. These four magnetic transistors as ordinary transistors that can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic... | 10/14/2008 |
| 7436207 | Integrated circuit device having at least one of a plurality of bond pads with a selectable plurality of input-output functionalities An integrated circuit device having at least one bond pad is coupled to a selectable plurality of input-output functionalities, e.g., an oscillator input, an analog input, an analog output, a digital input and a digital output. These analog, digital and oscillator f... | 10/14/2008 |
| 7432732 | Integrated circuit device including interface circuit and electronic apparatus An integrated circuit device, includes: an input pad region including a differential signal input region receiving a pair of differential signals, a first power supply input region and a second power supply input region; and an interface circuit including a receivin... | 10/07/2008 |
| 7428474 | Integrated circuit with self-proofreading function and measuring device using the same An integrated circuit (IC) includes a micro control unit (MCU), a one-time programmable (OTP) memory directly connected with the MCU, an electrical charge pump having an output port and an enable port connected to the MCU, and a switching circuit having a control po... | 09/23/2008 |
| 7425842 | Logic basic cell A logic basic cell for processing a first and a second data signal, having a multiplex device for multiplexing the first and second data signals in a multiplex operating state, having a logic device for forming a logic combination of the first and second data signal... | 09/16/2008 |
| 7420389 | Clock distribution in a configurable IC Some embodiments of the invention provide a reconfigurable IC that has several reconfigurable circuits. Each reconfigurable circuit for configurably performing a set of operations and for reconfiguring at a first frequency. The reconfigurable IC also has at least on... | 09/02/2008 |
| 7417462 | Variable external interface circuitry on programmable logic device integrated circuits A programmable logic device (“PLD”) includes circuitry for optionally and variably modifying characteristics of an input signal in any of several respects. Examples of such modifications include AC coupling the signal into the PLD, low pass filtering the signal ... | 08/26/2008 |
| 7414427 | Integrated multi-function analog circuit including voltage, current, and temperature monitor and gate-driver circuit blocks An integrated multi-function analog circuit includes at least one MOSFET gate-drive circuit coupled to a first I/O pad. At least one voltage-sensing circuit is coupled to a second I/O pad. At least one current-sensing circuit is coupled to the second I/O pad and a t... | 08/19/2008 |
| 7414429 | Integration of high-speed serial interface circuitry into programmable logic device architectures The architecture of a programmable logic device (“PLD”) is modified in one or more of several respects to facilitate inclusion of high-speed serial interface (“HSSI”) circuitry in the PLD. For example, the HSSI circuitry is preferably located along one side ... | 08/19/2008 |
| 7405587 | Interface circuit with a terminator and an integrated circuit and an electronic equipment having the same Provided is an interface circuit having a terminator, in which the terminator includes parallel-connected first to an Nth resistance elements, where N is an integral number equal to or more than 2, and a first to an nth cut-off elements connect... | 07/29/2008 |
| 7405590 | Systems and methods for controlling a fuse programming current in an IC Systems and methods for controlling the programming current directed through a fuse or set of fuses in a device such as an integrated circuit. One embodiment comprises a method for applying different currents to a set of calibration fuses, identifying which currents... | 07/29/2008 |
