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| Number | Title | Issue Date |
| 7367119 | Method for forming a reinforced tip for a probe storage device Systems and methods in accordance with the present invention can include a tip contactable with a media. In an embodiment, the tip comprises a substantially hollow structure formed of a metal. The tip can be formed by depositing a first metal layer over silicon ther... | 05/06/2008 |
| 7355435 | On-chip detection of power supply vulnerabilities On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outs... | 04/08/2008 |
| 7342423 | Circuit and method for calculating a logical combination of two input operands A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle, a second input for receiving a... | 03/11/2008 |
| 7336524 | Atomic probes and media for high density data storage A device in accordance with embodiments of the present invention comprises a contact probe for high density data storage reading, writing, erasing, or rewriting. In one embodiment, the contact probe can include a silicon core having a conductive coating. Contact pro... | 02/26/2008 |
| 7318169 | Fault tolerant computer A new method for the detection and correction of errors or faults induced in a computer or microprocessor caused by external sources of single event upsets (SEU). This method is named Time-Triple Modular Redundancy (TTMR) and is based upon the idea that very long in... | 01/08/2008 |
| 7309630 | Method for forming patterned media for a high density data storage device Systems in accordance with the present invention can include a tip contactable with a media, the media including a substrate and a plurality of cells disposed over the substrate, one or more of the cells being electrically isolated from the other of the cells by a m... | 12/18/2007 |
| 7301887 | Methods for erasing bit cells in a high density data storage device Methods in accordance with the present invention can be applied, in an embodiment, to a media comprising a phase change material to alter a resolved portion of the phase change material to have a resistance different from a resistance of the bulk material. A tip hav... | 11/27/2007 |
| 7276932 | Power-gating cell for virtual power rail control Virtual power-gated cells (VPC) are configured with control circuitry for buffering control signals and a power-gated block (PGB) comprising two or more NFETs for virtual ground rail nodes and PFETs for virtual positive rail nodes. Each VPC has a control voltage inp... | 10/02/2007 |
| 7269212 | Low-latency equalization in multi-level, multi-line communication systems Low-latency equalization mechanisms for multi-PAM communication systems are disclosed that reduce delay and complexity in signal correction mechanisms. The equalization mechanisms tap into input signals for a multi-PAM signal driver, and compensate for attenuation a... | 09/11/2007 |
| 7260742 | SEU and SEFI fault tolerant computer A non-hardened processor is made fault tolerant to SEUs and SEFIs. A processor is provided utilizing time redundancy to detect and respond to SEUs. Comparison circuitry is provided in a radiation hardened module to provide special redundancy with the need to run add... | 08/21/2007 |
| 7249290 | Deskew circuit and disk array control device using the deskew circuit, and deskew method A deskew circuit includes, for clock and every bit of data, a variable delay circuit between a receiver that receives data and a flip-flop that first latches the data, in which a detecting pattern to detect a stable region for receiving data is repeatedly sent befor... | 07/24/2007 |
| 7237148 | Functional interrupt mitigation for fault tolerant computer A new method for the detection and correction of environmentally induced functional interrupts (or “hangs”) induced in computers or microprocessors caused by external sources of single event upsets (SEU) which propagate into the internal control functions, or ci... | 06/26/2007 |
| 7218138 | Efficient implementations of the threshold-2 function A circuit and a method for operating the circuit are disclosed. A first step of the method generally comprises generating a plurality of first intermediate signals in two parallel first operations each responsive to a respective half of a plurality of input signals.... | 05/15/2007 |
| 7215155 | Control circuits and methods including delay times for multi-threshold CMOS devices Multi-Threshold CMOS (MTCMOS) devices include a high threshold voltage current control switch that is responsive to a first control signal, a low threshold voltage logic circuit and a flip-flop that is configured to store data from the low threshold voltage logic ci... | 05/08/2007 |
| 7212062 | Power supply noise insensitive multiplexer CMOS circuitry used to multiplex between data inputs suffers from high sensitivity to power supply noise, resulting in delay variations. By utilizing current controlled inverters in a multiplexer structure, power supply insensitivity can be achieved with either of t... | 05/01/2007 |
| 7157934 | Programmable asynchronous pipeline arrays High-performance, highly pipelined asynchronous FPGAs employ a very fine-grain pipelined logic block and routing interconnect architecture. These FPGAs, which do not use a clock to sequence computations, automatically “self-pipeline” their logic without the desi... | 01/02/2007 |
| 7138651 | Logic apparatus and logic circuit A logic apparatus comprises a first single-electron device formed of a first conductive island, two first tunnel barriers with the first conductive island interposed, first and second electrodes, and a first charge storage region, and a second single-electron device... | 11/21/2006 |
| 7133949 | Distributed switching method and apparatus Switching method and apparatus for assigning a communication grant to a first processing unit in a communication network comprising a plurality of processing units, each processing unit being connected to each other processing unit of the plurality of processing uni... | 11/07/2006 |
| 7129742 | Majority logic circuit A novel majority logic circuit is disclosed to determine whether the majority of the inputs are a one, within a constant number of clock cycles, regardless of the number of inputs. The majority logic circuit according to the present invention includes a plurality of... | 10/31/2006 |
| 7129741 | Semiconductor integrated circuit device, storage medium on which cell library is stored and designing method for semiconductor integrated circuit This invention provides a storage medium on which there is stored a cell library to design a semiconductor integrated circuit to satisfy low power consumption and high speed operation and a design method using the cell library. The cell library is registered with at... | 10/31/2006 |
| 7126408 | Method and apparatus for receiving high-speed signals with low latency An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time inter... | 10/24/2006 |
| 7103523 | Method and apparatus for implementing multiple configurations of multiple IO subsystems in a single simulation model A method and apparatus are provided for implementing multiple configurations of multiple input/output (IO) subsystems in a single simulation model. At least one bus routing switch is included in the single simulation model. Each bus routing switch includes a plurali... | 09/05/2006 |
| 7095262 | High reliability triple redundant latch with integrated testability In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memo... | 08/22/2006 |
| 7053804 | Phase-error reduction methods and controllers for time-interleaved analog-to-digital systems Methods and controllers are provided to estimate and reduce phase errors between converters of time-interleaved analog-to-digital systems by generating corresponding error signals in the form of difference signals. The difference signals concern differences between ... | 05/30/2006 |
| 7051127 | Method and apparatus for selectively providing data pre-emphasis based upon data content history The present invention comprises a method and apparatus for selectively providing pre-emphasis to the output of a first driver during an initial portion of certain data transitions while transmitting data along a data bus from a source to a destination, with the cert... | 05/23/2006 |
| 7042246 | Logic circuits for performing threshold functions Logic circuit generating four binary outputs as four threshold functions of four binary inputs, including: first, second, third, and fourth threshold functions which are respectively high if at least one, two, three and all of the binary inputs are high; first logic... | 05/09/2006 |
| 7036018 | Integrated security circuit An integrated security circuit, for example, a microcontroller for smart cards, includes a function unit executing a security function. A control device determines the number of executions of the security function per unit of time. The continued execution of the sec... | 04/25/2006 |
| 6978403 | Deskew circuit and disk array control device using the deskew circuit, and deskew method A deskew circuit includes, for clock and every bit of data, a variable delay circuit between a receiver that receives data and a flip-flop that first latches the data, in which a detecting pattern to detect a stable region for receiving data is repeatedly sent befor... | 12/20/2005 |
| 6972743 | Organic electroluminescent module An organic electroluminescent module is disclosed. The organic electroluminescent module comprises a plurality of scan lines, a plurality of data lines perpendicular to the plurality of scan lines, a plurality of light emitting diodes formed at cross regions of the ... | 12/06/2005 |
| 6965262 | Method and apparatus for receiving high speed signals with low latency An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time inter... | 11/15/2005 |
| 6956423 | Interleaved clock signal generator having serial delay and ring counter architecture The interleaved clock generator generates N interleaved clock signals in response to an input clock signal. The interleaved clock generator comprises an interleaved clock generator of a first type for receiving the input clock signal and for generating M interleaved... | 10/18/2005 |
| 6937053 | Single event hardening of null convention logic circuits A system and method for hardening a Null Convention Logic (NCL) circuit against Single Event Upset (SEU) is presented. Placing a resistive element into a feedback loop of the NCL circuit may harden the NCL circuit. A bypass element may be placed in parallel with the... | 08/30/2005 |
| 6907544 | Method for operating memory devices for storing data A storage device is disclosed and is characterized in that the data to be stored therein can be automatically and repeatedly stored in the device and/or in that additional information dependent on the data to be stored therein can be generated and stored in addition... | 06/14/2005 |
| 6907534 | Minimizing power consumption in pipelined circuit by shutting down pipelined circuit in response to predetermined period of time having expired Power consumption in a circuit is minimized. The circuit includes a pipelined circuit having a plurality of stages. A determination is made as to whether a predetermined period of time has expired. The predetermined period of time being associated with a predetermin... | 06/14/2005 |
| 6906388 | SEU hard majority voter for triple redundancy Majority voting between triple redundant integrated circuits is used in order to provide an SEU hardened output signal. Accordingly, an input signal is processed in a predetermined manner to provide a first signal, the input signal is processed in the same manner to... | 06/14/2005 |
| 6900658 | Null convention threshold gate A NULL convention-threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches it... | 05/31/2005 |
| 6888748 | Programmable circuit and its method of operation A programmable circuit and its method of operation are disclosed in which a transistor is used as a programmable element. The transistor may be programmed to one of two different gate threshold voltage values for operation. During reading of the transistor, a gate t... | 05/03/2005 |
| 6848094 | Netlist redundancy detection and global simplification A method of global simplification of a netlist for an integrated circuit includes steps for generating a variable set representative of the inputs and outputs of logic elements in the netlist, re-ordering the inputs and corresponding outputs of the logic elements in... | 01/25/2005 |
| 6828821 | Input buffer circuit An input buffer circuit includes front stage circuits and a succeeding stage circuit. Each of the front stage circuits has a logic threshold voltage different from each other. The succeeding stage circuit has a P type MOS transistor and an N type MOS transistor conn... | 12/07/2004 |
| 6798247 | Output buffer circuit An output buffer circuit disclosed herein includes a buffer supplied with an input signal and outputting an output signal from an output terminal; a driving assistant buffer including a first MISFET provided at one of a first position and a second position, the firs... | 09/28/2004 |
