Celebrity Inventors
Comic actor Danny Kaye received patent D166,807 for the co-design of "Blowout Toy or the Like". It's similar to one of those toys that unravels when you blow into at a birthday party except Kaye's has three blowouts going in different directions, not just one.
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| Number | Title | Issue Date |
| 8106678 | Semiconductor integrated circuits with power reduction mechanism A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching eleme... | 01/31/2012 |
| 8018247 | Apparatus and method for reducing power consumption using selective power gating A method and apparatus for reducing power consumption of transistor-based circuit is disclosed. The method includes receiving a low power mode indication; determining whether to supply power to at least a portion of the transistor-based circuit in response to a rese... | 09/13/2011 |
| 7928759 | Low power consumption MIS semiconductor device A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the su... | 04/19/2011 |
| 7834657 | Inverter circuit with compensation for threshold voltage variations An inverter circuit has a digital signal amplitude converter having an input coupled to an inverter circuit input node, and an amplitude converter output. A positive threshold voltage compensation generator has a positive threshold voltage compensation generator inp... | 11/16/2010 |
| 7821293 | Asynchronous interconnection system for 3D interchip communication An embodiment of the present invention relates to a asynchronous interconnection system comprising a transmitter circuit and a receiver circuit inserted between inserted between respective first and second voltage references and having respective transmitter and rec... | 10/26/2010 |
| 7741869 | Low power consumption MIS semiconductor device A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the su... | 06/22/2010 |
| 7705627 | Semiconductor device using power gating A semiconductor device using power gating includes a circuit unit and a current blocking unit. The circuit unit is connected between a first voltage node and a virtual voltage node. The current blocking unit is connected between the virtual voltage node and a second... | 04/27/2010 |
| 7667485 | Semiconductor integrated circuits with power reduction mechanism A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching eleme... | 02/23/2010 |
| 7486108 | Charge recycling power gate A charge recycling power gate and corresponding method are provided for using a charge sharing effect between a capacitive load of a functional unit and a parasitic capacitance of a charge recycling means to turn on a switching means between a virtual ground and a g... | 02/03/2009 |
| 7436206 | Semiconductor integrated circuit The present invention provides an integrated circuit capable of reducing a leak current and reliably holding data therein in a standby mode. A potential higher than a potential of a second source line is supplied to a first source line. A potential lower than a pote... | 10/14/2008 |
| 7400175 | Recycling charge to reduce energy consumption during mode transition in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuits In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a virtual ground node between the first circuit block and the first sleep transistor, a second circuit block connected to a supply via a second sleep transi... | 07/15/2008 |
| 7391233 | Method and apparatus for extending lifetime reliability of digital logic devices through removal of aging mechanisms An apparatus for extending lifetime reliability of CMOS circuitry includes a first switching device between a logic high supply rail/logic low supply rail, and a virtual supply rail coupled to the CMOS circuitry. In a first mode of operation the first switching devi... | 06/24/2008 |
| 7391230 | Adjustment of termination resistance in an on-die termination circuit The on-die termination circuit of the present invention includes a main resistance circuit and an adjustment circuit. The main resistance circuit is provided with a resistance element and a transistor that is turned OFF when the on-die termination circuit is to be p... | 06/24/2008 |
| 7391232 | Method and apparatus for extending lifetime reliability of digital logic devices through reversal of aging mechanisms An apparatus for extending lifetime reliability of CMOS circuitry includes a logic high supply rail, a logic low supply rail, and a virtual supply rail. In an intense recovery mode of operation, a first switching device is rendered nonconductive so as to isolate the... | 06/24/2008 |
| 7388400 | Semiconductor integrated circuits with power reduction mechanism A semiconductor integrated circuit with an operating voltage having an absolute value is 2.5 V or below includes circuit blocks to which operation voltage is supplied by first and second power lines and a first switching element for each circuit block. Each circuit ... | 06/17/2008 |
| 7382159 | High voltage input buffer An input buffer circuit includes a voltage limiting circuit and a protection circuit coupled between a pull-up component and a pull-down component of a level detecting circuit. The voltage limiting circuit receives an input signal at a first voltage range and limits... | 06/03/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7372721 | Segmented column virtual ground scheme in a static random access memory (SRAM) circuit A static random access memory (SRAM) cell array is provided that reduces leakage current. The SRAM cell array is configured in a plurality of columns. Each of the columns comprises: a column virtual ground node; a column switch for selectively coupling the column vi... | 05/13/2008 |
| 7368937 | Input termination circuits and methods for terminating inputs An input signal provided to an input terminal is terminated by coupling the input terminal to a ground voltage through a pull down transistor if the input signal at the input terminal is at a “high” level and coupling the input terminal to a power voltage throug... | 05/06/2008 |
| 7370293 | Integrated circuit design system, integrated circuit design program, and integrated circuit design method An integrated circuit design system able to generate circuit data enabling a clear grasp of power switch cells and circuit cells whose power is cut off without obstructing the efficiency of the design, a method of same, and a program of same, wherein in the descript... | 05/06/2008 |
| 7368938 | Input termination circuitry with high impedance at power off An input termination circuit includes a first and a second resistor each having a terminal respectively coupled to a first and a second input terminal of the input termination circuit, a first and a second transistor coupled in series between the first resistor and ... | 05/06/2008 |
| 7358770 | Driver circuit A circuit includes a first driver, a second driver, and a transformer coupled to the first and second driver. In operation, the first driver receives a first signal from a first input port, the second driver receives a time-delayed version of the first signal from a... | 04/15/2008 |
| 7342411 | Dynamic on-die termination launch latency reduction Embodiments of the invention are generally directed to systems, methods, and apparatuses for dynamic on-die termination launch latency reduction. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and a termination... | 03/11/2008 |
| 7332954 | Eased gate voltage restriction via body-bias voltage governor An arrangement, to ease restriction upon gate voltage (Vgg) magnitudes for a dynamic threshold MOS (DTMOS) transistor, may include: an MOS transistor including a gate and a body; and a body-bias-voltage (Vbb) governor (Vbb-governor) circuit to provide a governed ver... | 02/19/2008 |
| 7330047 | Receiver circuit arrangement having an inverter circuit A receiver circuit arrangement includes a receiver circuit an input for receiving an input signal an output for outputting an output signal and an inverter circuit with switching transistors. The input signal is fed to the receiver circuit. At least one control tran... | 02/12/2008 |
| 7319357 | System for controlling switch transistor performance The present invention provides a system for controlling performance of a switch transistor (106)—one that is implemented within a circuitry segment (100) to shut off a circuitry component (116) when that component is not in use. The switch tra... | 01/15/2008 |
| 7317334 | Voltage translator circuit and semiconductor memory device A voltage translator circuit capable of operating at high speed, saving the power consumption, and forming to have a smaller circuit area. When the output level of a decoder 110 is changed from the potential GND to the potential VDD, a pMOS transistor 125 ... | 01/08/2008 |
| 7302011 | Quadrature frequency doubling system The frequency doubler of the present invention operates to provide an in-phase signal and a quadrature signal, each having a frequency equal to twice the frequency of a reference signal. The in-phase and quadrature signals are based on signals that are 0 degrees, 45... | 11/27/2007 |
| 7295036 | Method and system for reducing static leakage current in programmable logic devices A programmable logic device having logic block that can be selectively placed in a reduced power consumption mode is provided. The PLD includes a plurality of logic array blocks (LABs) and a plurality of interconnects defining signal pathways between the plurality o... | 11/13/2007 |
| 7288968 | Circuit element A circuit element comprising N paired complementary transistors. The transistors are connected to an upper (VDD) and lower voltage level (VSS), in such a way that the paired transistors operate in subthreshold. N input terminals (X1,... | 10/30/2007 |
| 7288971 | Systems and methods for actively-peaked current-mode logic A method and apparatus for creating high speed logic circuits in a CMOS environment using current steering logic cells with actively-peaked NMOS or PMOS loads and the biasing of these logic cells is disclosed. The logic cells can include, for example, buffers, AND g... | 10/30/2007 |
| 7285977 | Impedance control circuits and methods of controlling impedance A circuit for controlling impedance may include an impedance adjustment circuit and a control signal generation circuit. The impedance adjustment circuit may adjust an impedance value based on a control signal. The control signal generation circuit may provide the i... | 10/23/2007 |
| 7279934 | Apparatus for delivering inputted signal data An apparatus for receiving an inputted signal in order to transmit the inputted signal from an external circuit to an internal circuit includes a comparing block, enabled by an enable signal, for outputting a logic value to the internal circuit in response to a volt... | 10/09/2007 |
| 7271615 | Integrated circuits with reduced leakage current In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Simil... | 09/18/2007 |
| 7259986 | Circuits and methods for providing low voltage, high performance register files Circuits and methods are provided to implement low voltage, higher performance semiconductor memory devices such as CMOS static random access memory (SRAM) or multi-port register files. For example, circuits and methods are provided for dynamically adjusting power s... | 08/21/2007 |
| 7256639 | Systems and methods for integrated circuits comprising multiple body bias domains Systems and methods for integrated circuits comprising multiple body bias domains. In accordance with a first embodiment of the present invention, an integrated circuit is constructed comprising active semiconductor devices in first and second body bias domains. A f... | 08/14/2007 |
| 7252085 | Device for inhalation therapy The invention relates to a device for inhalation therapy. Said device comprises an aerosol-producing device for spraying a liquid (3), preferably comprising a membrane (1), a support unit (6), an electromechanical transducer unit (7), and... | 08/07/2007 |
| 7248080 | Power supply switching at circuit block level to reduce integrated circuit input leakage currents Leakage currents at IC inputs can be avoided while the IC is disabled by providing a switch that is responsive to deactivation of an enable input to isolate functional circuitry of the IC from one of the power supply nodes of the IC. This eliminates power supply cur... | 07/24/2007 |
| 7242214 | Semiconductor integrated circuits with power reduction mechanism Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage c... | 07/10/2007 |
| 7236011 | High-speed differential logic buffer A circuit for a high speed digital buffer has an active load circuit connected to an output of the digital buffer. The active load circuit loads the buffer output with an active inductance to reduce the RC time constant at the buffer output. The active load circuit ... | 06/26/2007 |
