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| Number | Title | Issue Date |
| 8138786 | Apparatus and methods for adjusting performance of integrated circuits A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor wi... | 03/20/2012 |
| 7982494 | Systems and methods for detecting terminal state and setting output driver impedance Embodiments of the present invention include systems for calibrating an output circuit. A comparator is coupled to a calibration terminal and configured to determine whether the calibration terminal is in a first state coupled to a calibration resistor or in a secon... | 07/19/2011 |
| 7952385 | Temperature variance nullification in an inrush current suppression circuit The temperature dependence of an inrush current suppression circuit comprising a MOSFET having an input terminal coupled to a direct current input voltage can a transistor electrically coupled to the MOSFET can be reduced by matching the temperature coefficient of a... | 05/31/2011 |
| 7930658 | Semiconductor integrated circuit device and fabrication method thereof A semiconductor integrated circuit device and a fabrication method thereof are disclosed, for effective suppression of a temperature increase therein that is caused by heat generation of a semiconductor element. The semiconductor integrated circuit device includes a... | 04/19/2011 |
| 7902860 | Semiconductor circuit, and computing device and communications device using the same In a semiconductor circuit, an impedance adjustment circuit having the characteristics same as those of a circuit having the nonlinear resistance characteristics is configured to include an operating point calculation circuit automatically calculating an operating p... | 03/08/2011 |
| 7830168 | Temperature variance nullification in an inrush current suppression circuit The temperature dependence of an inrush current suppression circuit comprising a MOSFET having an input terminal coupled to a direct current input voltage can a transistor electrically coupled to the MOSFET can be reduced by matching the temperature coefficient of a... | 11/09/2010 |
| 7714608 | Temperature-independent, linear on-chip termination resistance In one embodiment, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for proces... | 05/11/2010 |
| 7696778 | Systems and methods for detecting terminal state and setting output driver impedance Embodiments of the present invention include systems for calibrating an output circuit. A comparator is coupled to a calibration terminal and configured to determine whether the calibration terminal is in a first state coupled to a calibration resistor or in a secon... | 04/13/2010 |
| 7663399 | Semiconductor memory device having output drive and delay unit An output driver for use in a semiconductor memory device includes a pull-up metal oxide semiconductor (MOS) transistor for pulling-up a voltage loaded on an output node in response to a pull-up control signal; a pull-up linear element connected between the pull-up ... | 02/16/2010 |
| 7586325 | Integrated circuit having independent voltage and process/temperature control In one embodiment, an integrated circuit has configurable application circuitry that operates at any one of multiple available power supply voltages. PT-control circuitry, operating at a PT reference voltage, generates a PT-control signal indicative of variations in... | 09/08/2009 |
| 7550993 | Glitch reduced compensated circuits and methods for using such Various embodiments of the present invention provide systems and methods for glitch reduced circuits. As one example, a glitch reduced, variable width driver circuit is disclosed. Such circuits include a data output, and at least two transistors that each includes a... | 06/23/2009 |
| 7511531 | Temperature-compensated output buffer A temperature-compensated output buffer circuit is disclosed, which includes a pull-up circuit including a first pull-up transistor for providing a first pull-up output signal responsive to a pull-up input signal, and a supplemental pull-up circuit in parallel with ... | 03/31/2009 |
| 7439759 | Operating long on-chip buses As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to po... | 10/21/2008 |
| 7414426 | Time multiplexed dynamic on-die termination Embodiments of the invention are generally directed to systems, methods, and apparatuses for time-multiplexed dynamic on-die termination. In an embodiment, an integrated circuit receives, during a first clock, an on-die termination (ODT) activation signal at its ODT... | 08/19/2008 |
| 7414427 | Integrated multi-function analog circuit including voltage, current, and temperature monitor and gate-driver circuit blocks An integrated multi-function analog circuit includes at least one MOSFET gate-drive circuit coupled to a first I/O pad. At least one voltage-sensing circuit is coupled to a second I/O pad. At least one current-sensing circuit is coupled to the second I/O pad and a t... | 08/19/2008 |
| 7403034 | PVT controller for programmable on die termination Embodiments include an on die termination circuit. The on die termination circuit may be programmable. The on die termination circuit may be programmed to compensate for environmental conditions and the physical characteristics of the device. The programmed on die t... | 07/22/2008 |
| 7397270 | Dynamically-adjustable differential output drivers Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuit... | 07/08/2008 |
| 7394283 | CML to CMOS signal converter A signal regenerator is provided which includes a common mode reference generator and a signal converter circuit. A common mode reference voltage level is generated which is variable in relation to at least one of a process used to fabricate the common mode referenc... | 07/01/2008 |
| 7391230 | Adjustment of termination resistance in an on-die termination circuit The on-die termination circuit of the present invention includes a main resistance circuit and an adjustment circuit. The main resistance circuit is provided with a resistance element and a transistor that is turned OFF when the on-die termination circuit is to be p... | 06/24/2008 |
| 7388398 | Inverter, NAND gate, and NOR gate irrelative to voltage, temperature, and process with an adjustable threshold An inverter with adjustable threshold and irrelative to voltage, temperature, and process is disclosed. The inverter includes an input end for receiving an input signal; an output end for outputting an inverted signal of the input signal; a first PMOS whose gate is ... | 06/17/2008 |
| 7385415 | Semiconductor integrated circuit A semiconductor integrated circuit for matching the resistance of a variable resistor, which is used as a terminating resistor or a reference of said terminating resistor, to the characteristic impedance of a transmission line, has a terminating resistor adjusting c... | 06/10/2008 |
| 7385414 | Impedance controllable ouput drive circuit in semiconductor device and impedance control method therefor A drive circuit having impedance control includes an impedance matching array unit having a plurality of transistors, the plurality of transistors selectively driven in accordance with an array drive control signal generated by control code data, and an update prohi... | 06/10/2008 |
| 7368937 | Input termination circuits and methods for terminating inputs An input signal provided to an input terminal is terminated by coupling the input terminal to a ground voltage through a pull down transistor if the input signal at the input terminal is at a “high” level and coupling the input terminal to a power voltage throug... | 05/06/2008 |
| 7362131 | Integrated circuit including programmable logic and external-device chip-enable override control An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring i... | 04/22/2008 |
| 7362147 | Integrated circuit An integrated circuit is disclosed that includes a MOS output stage transistor, a gate terminal for applying a drive signal, which controls the turning on and off of the output stage transistor, a charge transistor, which when the output stage transistor is turned o... | 04/22/2008 |
| 7355907 | Performing read and write operations in the same cycle for an SRAM device A decoding signal circuit is configured to generate a dual operation decoding signal that enables a read operation and a write operation to be performed in one clock cycle. The decoding signal circuit is configured such that a read decoding signal and a write decodi... | 04/08/2008 |
| 7353409 | System and method to maintain data processing system operation in degraded system cooling condition A method, computer program product, and a data processing system for maintaining operation of the data processing system in the event of a degraded system cooling condition is provided. A first temperature of a processor is identified as equaling or exceeding a proc... | 04/01/2008 |
| 7348827 | Apparatus and methods for adjusting performance of programmable logic devices A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmab... | 03/25/2008 |
| 7342411 | Dynamic on-die termination launch latency reduction Embodiments of the invention are generally directed to systems, methods, and apparatuses for dynamic on-die termination launch latency reduction. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and a termination... | 03/11/2008 |
| 7339399 | Anti-noise input/output impedance control of semiconductor circuit with reduced circuit size An impedance control system is composed of a target circuit having a controllable impedance; a replica circuit having a structure identical to the target circuit; a first binary counter providing the replica circuit with a first impedance control code indicative of ... | 03/04/2008 |
| 7336096 | System for transmission line termination by signal cancellation A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a ... | 02/26/2008 |
| 7332933 | Circuit for compensating for the declination of balanced impedance elements and a frequency mixer Provided is a circuit for compensating for the declination of balanced impedance elements and a frequency mixer. The compensation circuit compensates for a difference between impedance measured at first and second impedance elements, and comprises first and second i... | 02/19/2008 |
| 7321613 | Automatic impedance matching compensation for a serial point to point link An integrated circuit (IC) device that has an analog front end with an I/O buffer is reset. The I/O buffer has a driver circuit to transmit a stream of information over a serial point to point link, and a receiver circuit to receive a stream of information over the ... | 01/22/2008 |
| 7312629 | Programmable impedance control circuit calibrated at Voh, Vol level A method and apparatus are provided for a programmable impedance control circuit. In one example of the apparatus, a programmable impedance control circuit of an output driver of an input/output interface is provided. The programmable impedance control circuit inclu... | 12/25/2007 |
| 7282972 | Bias generator with feedback control A bias generator for initializing a voltage controlled delay line by providing the voltage controlled delay line with a control signal having an initial voltage and monitoring the variable delay line for an output clock signal. The voltage of the control signal is v... | 10/16/2007 |
| 7271755 | Resistor ladder interpolation for PGA and DAC A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at thei... | 09/18/2007 |
| 7259585 | Selective on-die termination for improved power management and thermal distribution A system, method and device for managing power distribution on a shared bus system that interconnects multiple devices each containing a signal termination component are disclosed herein. In one embodiment, the method of the invention includes detecting and communic... | 08/21/2007 |
| 7239172 | Impedance matching There is provided apparatus for connecting between a data source or a data receiver and a data line. The apparatus comprises an impedance and an impedance controller arranged to continually adjust the value of the active impedance so as to control the relative imped... | 07/03/2007 |
| 7236004 | Low voltage differential signaling with output differential voltage to output offset voltage tracking Apparatus and method for providing reference voltages for differential signaling with tracking of output differential voltage relative to output offset voltage are described. A swing reference voltage, an offset reference voltage, a swing feedback voltage, and an of... | 06/26/2007 |
| 7233471 | Circuit output stage protection system An output stage protection system for protecting NMOS devices in an integrated circuit (IC) output stage during normal operations and power up/power down. In an embodiment, the output stage includes a pair of relatively low voltage NMOS devices coupled to a current ... | 06/19/2007 |
