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3M employee and church chorister Art Fry needed something to temporarily mark pages in his hymnal. He was in luck because his colleague, Spencer Silver, accidentally developed a glue that was too weak for other purposes. After initially discouraging consumer response, Post-it Notes became a hit in 1979.
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| Number | Title | Issue Date |
| 8108817 | Semiconductor structure and method of designing semiconductor structure to avoid high voltage initiated latch-up in low voltage sectors Method and semiconductor structure to avoid latch-up. Method includes identifying at least one high voltage device on a semiconductor chip, identifying a circuit on the semiconductor chip separated from the identified at least one high voltage device by a guard ring... | 01/31/2012 |
| 7952384 | Data transmitter and related semiconductor device A semiconductor device transmitting a plurality of data using a multilevel signal includes a parity bit control unit generating a parity bit that varies with a number of data in which a most significant bit (MSB) and least significant bit (LSB) are different. A data... | 05/31/2011 |
| 7786755 | Reducing errors in data by dynamically calibrating trigger point thresholds Methods, systems, computer readable media and means for reducing errors in data caused by noise are provided. In some embodiments of the present invention, circuitry of the device receives timing data from one or more other circuitries and identifies noiseless perio... | 08/31/2010 |
| 7750667 | Semiconductor integrated circuit A semiconductor integrated circuit includes a MOS logic operating by first and second voltages; a switching transistor unit disposed between a supply terminal of the first voltage or the second voltage and the MOS logic, and turned on or off in response to a control... | 07/06/2010 |
| 7573290 | Data output driver for reducing noise A data input/output driver for use in a semiconductor memory device includes a data transmitting block for transmitting a data between an inside and an outside of the semiconductor memory device and generating a data driving signal in order to indicate a timing of o... | 08/11/2009 |
| 7463054 | Data bus charge-sharing technique for integrated circuit devices A data bus charge-sharing technique for integrated circuit devices may be implemented utilizing two voltage regulators to generate constant voltages VEQ1 and VEQ2, which are in the particular exemplary implementation disclosed, approximately 0.9 times ... | 12/09/2008 |
| 7439762 | On-die termination circuit An on-die termination circuit includes: a feedback unit for outputting a feedback signal in response to a plurality of code signals corresponding to an input-resistor; a code signal generation unit for generating the plurality of code signals in order for the feedba... | 10/21/2008 |
| 7439759 | Operating long on-chip buses As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to po... | 10/21/2008 |
| 7436206 | Semiconductor integrated circuit The present invention provides an integrated circuit capable of reducing a leak current and reliably holding data therein in a standby mode. A potential higher than a potential of a second source line is supplied to a first source line. A potential lower than a pote... | 10/14/2008 |
| 7429871 | Device for controlling on die termination An on die termination (ODT) control device includes a mode register set for generating a clock control signal based on mode set information; a clock control unit for receiving an internal clock signal and a delay locked loop (DLL) clock signal and outputting an inte... | 09/30/2008 |
| 7428465 | Testing control methods for use in current management systems for digital logic devices Systems and methods for Current Management of Digital Logic Devices are provided. In one embodiment a method for calibrating a digital logic circuit current management system is provided. The method comprises activating one or more synchronous logic paths of a plura... | 09/23/2008 |
| 7409659 | System and method for suppressing crosstalk glitch in digital circuits A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net, and the net is examined if crosstalk glitch induced in the selected victim net is sufficiently suppressed.... | 08/05/2008 |
| 7400165 | Method for calibrating a driver and on-die termination of a synchronous memory device An improved driver and ODT impedance calibration techniques of a synchronous memory device are provided. The impedance calibration is performed by generating a calibration enable signal showing a calibration operation mode entry. The code signals for an ODT calibrat... | 07/15/2008 |
| 7388404 | Driver circuit that limits the voltage of a wave front launched onto a transmission line A driver circuit limits the magnitude of the initial wave front launched onto a transmission line to a voltage that is approximately one-half of the supply voltage. Thus, immediately after the initial wave front is reflected from an open circuit receiver, a voltage ... | 06/17/2008 |
| 7372301 | Bus switch circuit and interactive level shifter A bus switch circuit includes a switch element having two terminals whose electrical connection is controlled when a control signal is input into a control terminal. The bus switch circuit further includes a first pull-up resistor and first switch circuit, a second ... | 05/13/2008 |
| 7372293 | Polarity driven dynamic on-die termination Embodiments of the invention are generally directed to systems, methods, and apparatuses for polarity driven on-die termination. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and an on-die termination (ODT) pi... | 05/13/2008 |
| 7372291 | Circuits having precision voltage clamping levels and method A slew rate control circuit includes a receiver for receiving input signals and an output generator for generating output signals based on the input signals. The slew rate control circuit also includes an electrical interconnection coupling an output of the receiver... | 05/13/2008 |
| 7365585 | Apparatus and method for charge pump slew rate control An apparatus and method for improving memory cell reliability is disclosed. The slew rate is reduced in an applied voltage signal used to program a memory cell when Fowler-Nordheim (FN) tunneling injection is detected. The applied programming signal is provided by a... | 04/29/2008 |
| 7358770 | Driver circuit A circuit includes a first driver, a second driver, and a transformer coupled to the first and second driver. In operation, the first driver receives a first signal from a first input port, the second driver receives a time-delayed version of the first signal from a... | 04/15/2008 |
| 7352755 | Network interface card (NIC) with phase lock rise time control generating circuit A Network Interface Card (NIC) for attaching data terminal equipment to a communications network. The NIC includes a Phase Lock Loop (PLL) with a master delay structure that is operatively coupled to at least one delay line structure. The PLL generates control pulse... | 04/01/2008 |
| 7342447 | Systems and methods for driving an output transistor A system and method is provided for driving an output transistor. The system and method employ a sense control to adjust a drive strength associated with driving the output transistor. The sense control measures an output parameter of the transistor, and adjusts the... | 03/11/2008 |
| 7337419 | Crosstalk noise reduction circuit and method In a semiconductor device, a method for reducing the effect of crosstalk from an aggressor line to a victim line begins with sensing the occurrence of a voltage change on the aggressor line that can induce a voltage pulse having a pulse magnitude that exceeds a puls... | 02/26/2008 |
| 7332937 | Dynamic logic with adaptive keeper Disclosed herein are solutions for providing adaptive keeper functionality to dynamic logic circuits. In some embodiments, a programmable keeper circuit is coupled to a register file circuit. Included is a leakage indicator circuit to model leakage in at least a por... | 02/19/2008 |
| 7330047 | Receiver circuit arrangement having an inverter circuit A receiver circuit arrangement includes a receiver circuit an input for receiving an input signal an output for outputting an output signal and an inverter circuit with switching transistors. The input signal is fed to the receiver circuit. At least one control tran... | 02/12/2008 |
| 7315182 | Circuit to observe internal clock and control signals in a receiver with integrated termination and common mode control A serial data receiver circuit includes a pair of differential input nodes, and receiver circuitry and a termination circuit coupled between the differential input nodes. The termination circuit comprises a common mode node. A common mode control circuit is connecte... | 01/01/2008 |
| 7312626 | CMOS circuits with reduced crowbar current Various circuit embodiments comprise an input node to receive an input signal for a CMOS transistor stack, a first output node to deliver the input signal to a PMOS pull-up transistor of the CMOS transistor stack, and a second output node to deliver the input signal... | 12/25/2007 |
| 7312629 | Programmable impedance control circuit calibrated at Voh, Vol level A method and apparatus are provided for a programmable impedance control circuit. In one example of the apparatus, a programmable impedance control circuit of an output driver of an input/output interface is provided. The programmable impedance control circuit inclu... | 12/25/2007 |
| 7301364 | Output buffer circuit and semiconductor device Disclosed is an output buffer circuit provided with a pre-emphasis function, including a first buffer circuit, receiving a first logic signal to drive a transmission line, and a second buffer circuit. The second buffer circuit includes an inverting buffer, receiving... | 11/27/2007 |
| 7302652 | Leakage control in integrated circuits Although there are a number of techniques available to reduce leakage current, there is still considerable room for improvement. Accordingly, the present inventors devised, among other things, an exemplary method which entails defining first and second leakage-reduc... | 11/27/2007 |
| 7282981 | Level conversion circuit with improved margin of level shift operation and level shifting delays To provide a level shift circuit in which the margin of level shift operation is prevented from deteriorating when the potential difference between a first power supply and a second power supply is large. A level shift circuit for changing the signal level in a firs... | 10/16/2007 |
| 7282959 | CMOS circuit including double-insulated-gate field-effect transistors It is an object of the present invention to provide a CMOS circuit implemented using four-terminal double-insulated-gate field-effect transistors, in which the problems described above can be overcome. Another object of the present invention is to reduce power consu... | 10/16/2007 |
| 7279927 | Integrated circuit with multiple power domains An integrated circuit having two or more power domains that include load circuits in different portions of the integrated circuit is disclosed. In order to conserve power, the circuits in one of the power domains are shut down by disconnecting the power source servi... | 10/09/2007 |
| 7259584 | Methods and structure for selective impedance control of bus driver circuits Methods and apparatus for selectively allowing and disallowing changes to an impedance control signal applied to bus driver circuits coupling a device or system to a common, shared bus where impedance of the bus may vary over time. Well known impedance sensing circu... | 08/21/2007 |
| 7253655 | Output driver robust to data dependent noise Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A... | 08/07/2007 |
| 7254169 | Method and apparatus for determining a loss of signal condition A loss-of-signal (LOS) condition is detected by sampling input data for a predetermined time period, comparing a magnitude of the sampled input data to a threshold signal strength level, and asserting a LOS indication if the number of samples that have signal streng... | 08/07/2007 |
| 7246018 | Interpolator testing circuit An interpolator testing system and method comprises an interpolator that includes a phase shift module. The phase shift module receives a reference clock signal and generates M clock signals having phase shifts in increments of 360/M degrees relative to the referenc... | 07/17/2007 |
| 7236002 | Digital CMOS-input with N-channel extended drain transistor for high-voltage protection A circuit and a method are given, to realize an electronic system for combined usage at differing voltage ranges as defined by a low-voltage range for operating standard CMOS devices and a high-voltage range exceeding said standard CMOS low-voltage operating range s... | 06/26/2007 |
| 7233166 | Bus state keepers Bus state keepers to maintain a steady state of an inactive bus to conserve power. In one embodiment of the invention, the bus state keepers include a plurality of multiplexers and a plurality of flip flops. The plurality of flip flops to store a state of a bus in r... | 06/19/2007 |
| 7218161 | Substantially temperature independent delay chain Methods and apparatuses are discussed for generating a temperature compensated signal, used for example to provide a signal with a delay within a pre-specified range over a range of temperatures to a sense amplifier of a memory array. In response to a start signal, ... | 05/15/2007 |
| 7218148 | Tracking unity gain for edge rate and timing control In general, in one aspect, the disclosure describes an apparatus for calibrating signals. The apparatus includes a unity gain detector to traverse a gain curve of an output buffer circuit to determine unity gain voltages associated with unity gain crossover points o... | 05/15/2007 |
