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| Number | Title | Issue Date |
| 8111084 | Impedance calibration circuit and semiconductor apparatus using the same An impedance calibration circuit includes: a first calibration unit configured to compare a first converted voltage obtained by converting a first calibration signal with a reference voltage and vary the first calibration signal; a voltage detection unit configured ... | 02/07/2012 |
| 8111085 | Semiconductor integrated circuit, semiconductor storage device and impedance adjustment method It is desired to reduce the current consumption of an autonomous impedance adjustment circuit. The semiconductor integrated circuit according to the present invention stops the change in the drive capability of a driver correspondingly to the output (count data) of ... | 02/07/2012 |
| 8106676 | Semiconductor device A semiconductor device includes a signal generating circuit that generates an impedance adjustment command signal which indicates at least one of initiation and termination of an impedance adjustment. The semiconductor device outputs an output signal in synchronism ... | 01/31/2012 |
| 8106677 | Signal transmitting device suited to fast signal transmission A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting ... | 01/31/2012 |
| 8102186 | Semiconductor integrated circuit with first and second transmitter-receivers Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a... | 01/24/2012 |
| 8089298 | Integrated circuit device with dynamically selected on-die termination In an integrated circuit device having dynamically selected on-die termination, a set of data inputs are coupled respectively to a set of termination circuits, each termination circuit having multiple controllable termination impedance configurations. A termination ... | 01/03/2012 |
| 8085062 | Configurable bus termination for multi-core/multi-package processor configurations A multi-core/multi-package bus termination apparatus includes a configuration array and a plurality of drivers. The configuration array generates location/protocol signals that each direct one of the plurality of drivers on the bus to employ location-based bus termi... | 12/27/2011 |
| 8085061 | Output circuit of semiconductor device An output circuit of a semiconductor includes unit buffers, each unit buffer having transistors and resistors connected between a power source terminal VDDQ and an output terminal DQ, and transistors and resistors connected between a power source terminal VSSQ and a... | 12/27/2011 |
| 8076954 | Memory control circuit, memory control method, and integrated circuit Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for... | 12/13/2011 |
| 8072235 | Integrated circuit with configurable on-die termination Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, ... | 12/06/2011 |
| 8067956 | Apparatus and method for calibrating on-die termination in semiconductor memory device An on-die termination circuit in a semiconductor memory apparatus can comprise a comparing block for comparing a reference voltage with a code voltage corresponding to a code and outputting a comparison signal, a counting block for changing the code based on the com... | 11/29/2011 |
| 8067957 | USB 2.0 HS voltage-mode transmitter with tuned termination resistance A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver ... | 11/29/2011 |
| 8063658 | Termination circuit for on-die termination In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor ... | 11/22/2011 |
| 8058895 | Single-resistor static programming circuits and methods A method of programming an integrated circuit to operate in a selected operating mode includes assigning different resistance values to correspond to different operating modes of the integrated circuit, wherein the different resistance values are non-zero finite val... | 11/15/2011 |
| 8054100 | Line transceiver apparatus for multiple transmission standards A line transceiver apparatus for multiple transmission standards including a operational amplifier (OP-AMP), a transformer unit, a first variable resistor unit to a sixth variable resistor unit, and a variable resistor control unit is provided. The first resistor an... | 11/08/2011 |
| 8049530 | Output impedance calibration circuit with multiple output driver models A method and circuitry for calibration of the output impedance of output driver circuits in an integrated circuit is disclosed. The output drivers within an area on the integrated circuit are defined as a group, and an output model indicative of the operation of the... | 11/01/2011 |
| 8044680 | Semiconductor memory device and on-die termination circuit An on-die termination (ODT) circuit including drive signal generators, each drive signal generator configured to generate a corresponding plurality of ODT drive signals; and ODT drive units, each ODT drive unit configured to terminate a corresponding terminal with a... | 10/25/2011 |
| 8044679 | On-die termination control circuit of semiconductor memory device On-die termination control circuit of semiconductor memory device includes a counter configured to count an external clock to output a first code, and to count an internal clock to output a second code, a transfer controller configured to determine whether to transf... | 10/25/2011 |
| 8040150 | Impedance adjustment circuit An impedance adjustment circuit according to the present invention includes a first input buffer which detects that an input signal exceeds VREFA, a second input buffer which detects that the input signal exceeds VREFB, VREFB being higher than VREFA, a counter circu... | 10/18/2011 |
| 8035412 | On-die termination latency clock control circuit and method of controlling the on-die termination latency clock A semiconductor device includes an on-die termination (ODT) latency clock control circuit and an ODT circuit controlled by the ODT latency clock control circuit. The ODT latency clock control circuit includes an ODT enable signal generator receiving an ODT signal in... | 10/11/2011 |
| 8035413 | Dynamic impedance control for input/output buffers A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode... | 10/11/2011 |
| 8030961 | Semiconductor integrated circuit A semiconductor integrated circuit includes a control signal generating circuit which is configured to set, at least at a time of a first state, first and fifth control signals at a first voltage level, and second, third and fourth control signals at a second voltag... | 10/04/2011 |
| 8022723 | Dynamic termination-impedance control for bidirectional I/O pins Circuits, methods, and apparatus for dynamic control of source and termination impedances. One output stage provides a series termination when transmitting and a parallel termination when receiving data. A pull-up device has a nominal impedance of 50 ohms when the o... | 09/20/2011 |
| 8018246 | Semiconductor device A device includes a first circuit and an adjustment circuit. The adjustment circuit performs an adjustment on impedance of the first circuit. The adjustment circuit discontinues the adjustment on impedance while the first circuit is in an activated state. ... | 09/13/2011 |
| 8008944 | Low voltage differential signaling driver with programmable on-chip resistor termination A low voltage differential signaling driver is disclosed and may include a current steering output circuit having a first driver output and a second driver output. The low voltage differential signaling driver may also include a programmable on-chip resistor. ... | 08/30/2011 |
| 8004308 | Techniques for providing calibrated on-chip termination impedance Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. Th... | 08/23/2011 |
| 7999568 | Techniques for serially transmitting on-chip termination control signals Techniques are provided for controlling on-chip termination (OCT) impedance using OCT calibration blocks that serially transmit OCT control signals to input/output (IO) blocks. The OCT control signals are serially transmitted through a shared conductor. An OCT calib... | 08/16/2011 |
| 7999569 | Edge rate suppression for open drain buses An edge rate suppression circuit arrangement is provided for operation with an open drain bus. The circuit arrangement includes a variable resistive circuit having an input for receiving a variable voltage signal and an output coupled to the open drain bus, and a co... | 08/16/2011 |
| 7994813 | Semiconductor device capable of testing a transmission line for an impedance calibration code A semiconductor device includes a plurality of pads, where an external reference resistor is connected to a first one of the pads, an impedance calibrating unit configured to generate an impedance calibration code corresponding to an impedance of the reference resis... | 08/09/2011 |
| 7994812 | Calibration circuit, semiconductor device including the same, and data processing system A semiconductor device adjusting an impedance level of an output buffer, includes a replica buffer circuit including a circuit configuration substantially identical to the output buffer, a counter circuit changing an impedance code to vary an impedance level of the ... | 08/09/2011 |
| 7994814 | Programmable transmitter Some embodiments of the present invention provide a programmable transmitter which includes a set of drivers and one or more chains of configuration registers. Each driver is capable of being configured to perform a transmission function from a predetermined set of ... | 08/09/2011 |
| 7990175 | Output buffer circuit and integrated circuit including same An output buffer circuit includes a control unit and an output driver. The control unit generates a control signal in response to a mode signal applied from an internal circuit. The output driver selectively performs a driver operation, a termination operation or an... | 08/02/2011 |
| 7990174 | Circuit for calibrating impedance and semiconductor apparatus using the same A circuit for calibrating impedance includes an enable signal generator, a code generator and a connection controller. The enable signal generator generates an enable signal in response to a chip selection signal. The code generator generates an impedance calibratio... | 08/02/2011 |
| 7986161 | Termination resistance circuit A termination resistance circuit includes a control signal generator for generating a control signal whose logical value changes when a calibration code has a predetermined value, a plurality of parallel resistors which are respectively turned on/off in response to ... | 07/26/2011 |
| 7986160 | Apparatus and methods for adjusting performance characteristics and power consumption of programmable logic devices A PLD includes at least one IP block or circuit, and at least one I/O block or circuit. The performance of the at least one IP block is adjusted in order to meet at least one performance characteristic by changing a supply level of the at least one IP block, by adju... | 07/26/2011 |
| 7982491 | Active termination and switchable passive termination circuits According to one exemplary embodiment, an active termination circuit includes at least one active termination branch, where the at least one active termination branch includes at least one transistor for providing an active termination output. The at least one activ... | 07/19/2011 |
| 7982492 | Adaptive termination A system for receiving data is provided. The system includes an inductive data device, such as a device that receives high-speed data over an inductive coupling. An adjustable impedance is coupled to the inductive data device, where the adjustable impedance is used ... | 07/19/2011 |
| 7982493 | Semiconductor integrated circuit for controlling output driving force A semiconductor integrated circuit includes a pre driver unit configured to receive a pre drive signal and a driving force control signal and output a main drive signal; a main driver unit configured to receive the main drive signal and output output data to an outp... | 07/19/2011 |
| 7977968 | Semiconductor memory device A semiconductor memory device includes a code channel for outputting a plurality of code signals based on a code control signal inputted from an external source; a termination resistor decoder for decoding a chip selection signal, an on die termination (ODT) control... | 07/12/2011 |
| 7973552 | On-die terminators formed of coarse and fine resistors An integrated circuit includes a semiconductor substrate; a first node; a second node; and a first plurality of resistors, each in a first plurality of resistor units. Each of the first plurality of resistor units includes a first end connected to the first node, an... | 07/05/2011 |
