Did You Know...
...that the Band-Aid Bandage was invented by a Johnson & Johnson employee whose wife had cut herself? Earl Dickson's wife was rather accident prone, so he set out to develop a bandage that she could apply without help. He placed a small piece of gauze in the center of a small piece of surgical tape, and what we know today as the Band Aid bandage was born!
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| Number | Title | Issue Date |
| 7675315 | Output stage with low output impedance and operating from a low power supply A low-impedance output stage which operates from a low voltage power supply. In an embodiment, the output stage contains an operational amplifier and two PMOS transistors used in a feedback configuration resulting in low output impedance. The output stage may also i... | 03/09/2010 |
| 7675316 | Semiconductor memory device including on die termination circuit and on die termination method thereof A semiconductor memory device is provided. The device includes an on die termination circuit controlling a termination resistance value by detecting a phase change of a signal inputted through a pad. Additionally, the on die termination circuit changes the terminati... | 03/09/2010 |
| 7671622 | On-die-termination control circuit and method On-die-termination control circuit includes a mode detecting unit for detecting a power-down mode and a power-down delay configured to delay an on/off control signal in the power-down mode. On-die-termination control circuit provided a shift register configured to d... | 03/02/2010 |
| 7667483 | Circuit and method for controlling termination impedance A calibration circuit that can prevent a calibration operation from being delayed by a dummy capacitor when the calibration circuit starts to operate includes a switch unit configured to connect a calibration node to a precharge node in response to an enable signal.... | 02/23/2010 |
| 7663397 | Semiconductor device including on-die termination control circuit having pipe line varying with frequency range A semiconductor device according to example embodiments that may include an on-die termination (ODT) control circuit having a pipe line structure which changes in response to a frequency of a clock signal and a termination resistance generator for generating termina... | 02/16/2010 |
| 7663398 | Circuit and method for high impedance input/output termination in shut off mode and for negative signal swing A circuit including control logic; and configurable impedance logic, operatively coupled to the control logic, comprising a configurable transistor structure operative to selectively change from a high impedance mode where the configurable transistor structure is co... | 02/16/2010 |
| 7656186 | Calibration circuit, semiconductor device including the same, and data processing system A calibration circuit includes: replica buffers; an up-down counter that changes impedance codes of the replica buffers; latch circuits each holding the impedance codes; an end-determining circuit that activates the latch circuits in response to a completion of impe... | 02/02/2010 |
| 7646214 | Power harvesting signal line termination In various embodiments of the invention, a power-harvesting termination circuit may be used to 1) match the impedance of a signal line being terminated, and 2) recover a portion of electrical power from a signal on the signal line and provide the recovered power as ... | 01/12/2010 |
| 7646215 | Efficient method for implementing programmable impedance output drivers and programmable input on die termination on a bi-directional data bus A combined input and termination circuit comprises a fixed portion of impedance and a programmable portion of impedance. The fixed portion is able to be fixed in a driver mode and a termination mode. The programmable portion is able to be configured to have a desire... | 01/12/2010 |
| 7646212 | Memory system including a power divider on a multi module memory bus A memory system includes a memory controller, a transmission bus, a power divider, a first memory chip, and a second memory chip. The transmission bus is coupled from the memory controller to a first node of the power divider for transferring signals. The first node... | 01/12/2010 |
| 7646213 | On-die system and method for controlling termination impedance of memory device data bus terminals A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a termination resistor connected to each data bus terminal, which is connected in parallel with several tra... | 01/12/2010 |
| 7642808 | Impedance adjusting circuit and semiconductor memory device having the same An impedance adjusting circuit includes: a first calibration resistor circuit configured to be calibrated with an external resistor and generate a first calibration code; a second calibration resistor circuit configured to be calibrated with the first calibration re... | 01/05/2010 |
| 7639038 | Terminating resistance adjusting method, semiconductor integrated circuit and semiconductor device A terminal resistance adjusting method adjusts a terminating resistance within a semiconductor integrated circuit. The method includes obtaining a comparison result by comparing a reference voltage and a voltage of a first node that is coupled to a first voltage via... | 12/29/2009 |
| 7633310 | Semiconductor integrated circuit capable of autonomously adjusting output impedance A semiconductor integrated circuit includes an output driver, a replica driver, a replica resistor, and an impedance adjustment circuit. The output driver is configured to be capable of changing current driving capability. The replica driver is configured to be capa... | 12/15/2009 |
| 7629811 | Control circuit for controlling on-die termination impedance The present invention relates to an ODT control circuit which is controlled in synchronization with an external clock during power-down mode. An ODT control circuit according to the present invention includes a clock control circuit which receives a synchronized int... | 12/08/2009 |
| 7626416 | Method and apparatus for high resolution ZQ calibration A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is to be connected such that a predetermined value of the voltage at the impedance control terminal controls ... | 12/01/2009 |
| 7626417 | On-die-termination control circuit and method On-die-termination control circuit includes a clock generator configured to generate shift clocks in response to an on/off control signal; and a shift register configured to delay the on/off control signal in synchronization with the shift clocks to control on/off t... | 12/01/2009 |
| 7622946 | Design structure for an automatic driver/transmission line/receiver impedance matching circuitry A design structure for an impedance matcher that automatically matches impedance between a driver and a receiver. The design structure for an impedance matcher includes a phase-locked loop (PLL) circuit that locks onto a data signal provided by the driver. The imped... | 11/24/2009 |
| 7619439 | Semiconductor device When a plurality of output buffer circuits are provided, chip layout size, power consumption, and number of pins of an LSI circuit are reduced. A voltage generation circuit generates reference voltages corresponding respectively to the output buffer circuits. A comp... | 11/17/2009 |
| 7612580 | Reduced power output buffer A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a pl... | 11/03/2009 |
| 7612578 | Semiconductor device, test system and method of testing on die termination circuit A semiconductor device, a test system and a method of testing an on die termination (ODT) circuit are disclosed. The semiconductor device includes an ODT circuit, a termination impedance control circuit and a boundary scan circuit. The termination impedance control ... | 11/03/2009 |
| 7612579 | Output circuit of semiconductor device and semiconductor device including thereof An output circuit includes a counter circuit that generates an ODT control signal ODTa, plural driver circuits having the ODT function, a synchronizing circuit that synchronizes a signal transmitted from the counter circuit to the driver circuit with an internal clo... | 11/03/2009 |
| 7602208 | On die termination device that can control terminal resistance An on die termination controls a terminal resistance value in accordance with a test signal. The one die termination device comprises an on die termination control unit and an on die termination resistor unit and can change the terminal resistance value in accordanc... | 10/13/2009 |
| 7602209 | Controlling memory devices that have on-die termination A memory controller for controlling integrated circuit memory devices that have on-die termination. The memory controller includes an output driver to output a first data signal onto a data line, and termination control circuitry to output termination control signal... | 10/13/2009 |
| 7595656 | Interface circuit and semiconductor integrated circuit An interface circuit includes a driver circuit (12) made up of a combination of a plurality of transistors, a calibration circuit (14) for performing selection of on and off of one or more of the plurality of transistors for adjusting on-resistance the... | 09/29/2009 |
| 7595657 | Dynamic dual control on-die termination Controlling on-die termination on a bi-directional single-ended data bus carrying data between a controller and a memory device. The controller and the memory device respectively include input termination pull-ups and input termination pull-downs. An enabled state i... | 09/29/2009 |
| 7589554 | I/O interface circuit of intergrated circuit A plurality of transistor pairs of Pch and Nch transistors are connected in series between VDD and GND. An I/O terminal is connected to each connection point of the transistor pairs. Two transistor pairs constitute one transistor set, in which each of two Pch transi... | 09/15/2009 |
| 7579862 | MOS linear region impedance curvature correction A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature while accommodating PVT spreads in values of internal or external precision resistors. The linear region... | 08/25/2009 |
| 7576560 | Apparatus for measuring on-die termination (ODT) resistance and semiconductor memory device having the same An apparatus for measuring an on-die termination (ODT) resistance includes an ODT controller and a driver. The ODT controller receives a plurality of decoding signals, a first test mode signal, and a second test mode signal to generate a plurality of pull-up signals... | 08/18/2009 |
| 7576559 | USB device and data processing system having the same A universal serial bus (USB) device is comprised of a receiver for receiving signals from a USB host through data lines, and a pull-up resistor circuit connecting pull-up resistors to data lines in response to control signals. The pull-up resistor circuit selectivel... | 08/18/2009 |
| 7573288 | Dynamically adjusting operation of a circuit within a semiconductor device Systems and methods for dynamically adjusting operation of a circuit within a semiconductor device are described herein. At least some illustrative embodiments include a system that includes a matching circuit including a first plurality of switching devices coupled... | 08/11/2009 |
| 7573289 | Impedance matching circuit and semiconductor memory device with the same An impedance matching circuit includes a code generating unit for generating a calibration code in response to a reference voltage and a voltage on a node, a calibration resistance unit for supplying a power supply voltage to the node, being calibrated to an externa... | 08/11/2009 |
| 7567093 | Semiconductor memory device with on-die termination circuit A semiconductor memory device is able to inactivate an on-die termination circuit without an additional pin. The semiconductor memory device includes a control signal generator, a resistance control unit, and a resistance supply unit. The control signal generator ge... | 07/28/2009 |
| 7564258 | Calibration methods and circuits to calibrate drive current and termination impedance Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates a... | 07/21/2009 |
| 7557603 | Method and apparatus for output driver calibration, and memory devices and system embodying same A method, system, and output driver calibration circuit determine calibration values for configuring adjustable impedance output drivers. The calibration circuit includes a pull-up calibration circuit configured to generate an averaged pull-up count signal for calib... | 07/07/2009 |
| 7554354 | Apparatus for controlling on-die termination of semiconductor memory and methods of controlling the same An apparatus for controlling on-die termination of a semiconductor memory includes a detector that generates an ODT control signal for inactivating an on-die termination operation in one of a data read period and a data write period in response to a command signal f... | 06/30/2009 |
| 7554353 | Method of controlling on-die termination of memory devices sharing signal lines A method of controlling On-Die Termination (ODT) resistors of memory devices sharing signal lines is provided. The ODT controlling method comprises setting an ODT control enable signal of each of the memory devices and address/command or data termination information... | 06/30/2009 |
| 7548086 | Impedance control circuit in semiconductor device and impedance control method An impedance control circuit includes an impedance detector, an output driver and an impedance controller. The impedance detector generates a first output value to a detection pad connected between an external determination resistor and a pull-up transistor array, a... | 06/16/2009 |
| 7548087 | Impedance adjusting circuit and impedance adjusting method An impedance adjusting circuit for adjusting an impedance of an output buffer of a DDR2 memory, using an OCD impedance adjusting function, from a side of a memory controller, includes first and second terminals, first and second switches, a comparator, and a control... | 06/16/2009 |
| 7545164 | Output driver for controlling impedance and intensity of pre-emphasis driver using mode register set An output driver controls impedance using a mode register set. The output driver includes a main driving circuit that outputs and drives a main signal based on a data signal to a predetermined transmission line, an auxiliary driving circuit that outputs and drives a... | 06/09/2009 |