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| Number | Title | Issue Date |
| 8183880 | Devices and methods for driving a signal off an integrated circuit Embodiments of the present invention provide electronic devices, memory devices and methods of driving an on-chip signal off a chip. In one such embodiment, an on-chip signal and a second signal complementary to the on-chip signal are generated and provided to the t... | 05/22/2012 |
| 8115508 | Structure for time based driver output transition (slew) rate compensation A design structure and more particularly to a design structure to minimize driver output slew rate variation. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes ... | 02/14/2012 |
| 8018245 | Semiconductor device A semiconductor device is provided. A pull-up slew rate controller receives a first driving control signal generated in a first mode of operation, a second driving control signal generated in a second mode of operation, and data, and upon a first transition of the d... | 09/13/2011 |
| 7940075 | Differential pre-emphasis driver Disclosed is a differential pre-emphasis driver. The driver includes a first current source supplying a first current, a second current source supplying a second current greater than the first current, a first select circuit for selectively connecting the first curr... | 05/10/2011 |
| 7924046 | Configurable emphasis for high-speed transmitter driver circuitry Pre-emphasis may be able to operate in either of two modes. In a first mode, when one bit has a same value as the bit that immediately preceded it, an output signal for said one bit is based on a first electrical current reduced by a second electrical current. Other... | 04/12/2011 |
| 7915911 | Input circuit and semiconductor integrated circuit An input circuit for receiving an input signal supplied to an input terminal includes a capacitor having one end connected to the input terminal and a capacitor driving circuit for converting the input signal into a signal having positive logic that is the same as l... | 03/29/2011 |
| 7859295 | Transmitter apparatus, systems, and methods Apparatus, systems, and methods are disclosed that operate to drive an output with a data signal and to boost a potential of the output in response to a boost signal. Additional apparatus, systems, and methods are disclosed. ... | 12/28/2010 |
| 7847583 | Transmitter and receiver using asymmetric transfer characteristics in differential amplifiers to suppress noise An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The different... | 12/07/2010 |
| 7808268 | Time based driver output transition (slew) rate compensation Apparatus controlling the driver output slew rate that includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A delay circuit having a ti... | 10/05/2010 |
| 7804322 | Output buffer An output buffer includes at least a first and a second stage, wherein each stage is formed by respective first transistors and second transistors coupled in series with each other between a first and a second voltage reference. The coupled first and second transist... | 09/28/2010 |
| 7795902 | Integrated circuit device with slew rate controlled output buffer An integrated circuit device includes an output buffer having a capacitance circuit configurable in a slew rate configuration or a decoupling configuration. In the slew rate configuration, the capacitance circuit electrically couples a capacitor of the capacitance c... | 09/14/2010 |
| 7786750 | Methods and apparatus for compensating for skew in a differential signal using non-complementary inverters Methods and apparatus are provided for compensating for skew in a differential signal using non-complementary inverters. A skew attenuator is provided for a differential signal having a P rail and an N rail. The skew attenuator comprises one or more non-complementar... | 08/31/2010 |
| 7733118 | Devices and methods for driving a signal off an integrated circuit Embodiments of the present invention provide electronic devices, memory devices and methods of driving an on-chip signal off a chip. In one such embodiment, an on-chip signal and a second signal complementary to the on-chip signal are generated and provided to the t... | 06/08/2010 |
| 7724025 | Leakage efficient anti-glitch filter A leakage efficient anti-glitch filter. In accordance with a first embodiment of the present invention, a leakage efficient anti-glitch filter with variable delay stages comprises a plurality of variable delay stages and a coincidence detector element for detecting ... | 05/25/2010 |
| 7719306 | Output buffer for an electronic device In order to reduce production cost, an output buffer for an electronic device includes a first logic unit, a second logic unit, a first transistor, a second transistor and a control unit. The first logic unit and the second unit are both coupled to an input terminal... | 05/18/2010 |
| 7705625 | Source transistor configurations and control methods Source transistor configurations are described for reducing leakage and delay within integrated circuits. Virtual power and ground nodes are supported with the use of stacked transistor configurations, such as a two transistor stack between a first virtual supply co... | 04/27/2010 |
| 7649380 | Logic circuits with electric field relaxation transistors and semiconductor devices having the same In a logic circuit, a first switching device is connected between a first voltage and an output terminal through which an output signal is output. The switching device is selectively activated and deactivated based on an input signal. A second switching device is co... | 01/19/2010 |
| 7609084 | Output level stabilization circuit and CML circuit using the same An output level stabilization circuit being an output level stabilization circuit for a CML circuit, the output level stabilization circuit includes: a replica circuit constituted of transistors respectively having the same characteristics as one of differential-pai... | 10/27/2009 |
| 7605602 | Low-power output driver buffer circuit In one embodiment, an output driver buffer circuit for a logic device includes an output driver transistor adapted to adjust an output voltage of an output pad; a capacitor adapted to be connected to the transistor gate and further adapted when charged and connected... | 10/20/2009 |
| 7592830 | Integrated circuit device for receiving differential and single-ended signals An integrated circuit device includes a receiver that is capable of receiving and converting either differential input signals or two unrelated single-ended input signals. ... | 09/22/2009 |
| 7592831 | Circuit to optimize charging of bootstrap capacitor with bootstrap diode emulator A circuit for optimizing charging of a bootstrap capacitor connected to a high side floating supply voltage at a first terminal and to a switched node voltage at a second terminal, the circuit for optimizing being included in a gate driver circuit having high- and l... | 09/22/2009 |
| 7579861 | Impedance-controlled pseudo-open drain output driver circuit and method for driving the same An impedance-controlled pseudo-open drain output driver circuit includes: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to out... | 08/25/2009 |
| 7573287 | Variable drive module for driving a load A drive module for driving a load is disclosed. In one embodiment, the drive module includes an output terminal for connecting the load. A first control terminal is provided for applying a first control signal, according to which the circuit arrangement provides a s... | 08/11/2009 |
| 7557602 | Pre-emphasis circuit including slew rate controllable buffer A pre-emphasis circuit capable of controlling the slew rate of a signal output from a buffer that transfers the output signal to an output driver to increase the range of a controllable voltage step includes a first buffer, a second buffer, and an output driver. The... | 07/07/2009 |
| 7521956 | Methods and apparatus for adaptively adjusting a data receiver Methods are provided to reduce offsets and timing skews in data signals captured in a data receiver by adaptively adjusting a transition threshold of the data receiver. A set of adjustment vectors for adjusting the transition threshold of the data receiver are gener... | 04/21/2009 |
| 7495465 | PVT variation detection and compensation circuit A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit includes a signal generator, a first code generator, a second code generato... | 02/24/2009 |
| 7489158 | Feedback circuit for line load compensation and reflection reduction Line load compensation and reflection reduction in a signal transmitting circuit is provided using feedback capacitors. The feedback capacitor serially coupled with a resistance generates an RC rise/fall time that is independent of the line load. Additionally, by se... | 02/10/2009 |
| 7486103 | Switching system capable of reducing noise of output signal A switching system capable of reducing the noise of the output signal is provided. The switching system includes a first switch and a second switch, wherein the first switch conducts a first signal according to a first control signal; the second switch conducts a se... | 02/03/2009 |
| 7463051 | Output buffer An output buffer includes at least a first and a second stage, wherein each stage is formed by respective first transistors and second transistors coupled in series with each other between a first and a second voltage reference. The coupled first and second transist... | 12/09/2008 |
| 7456648 | Differential amplifiers using asymmetric transfer characteristics to suppress input noise in output logic signals An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The different... | 11/25/2008 |
| 7443217 | Circuit and method to balance delays through true and complement phases of differential and complementary drivers A circuit for balancing delays through true and complement phases of complementary drivers includes: a first driver; a second driver; a first delay device coupled to an input of the first driver and having an input coupled to an input signal node; a second delay dev... | 10/28/2008 |
| 7439759 | Operating long on-chip buses As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to po... | 10/21/2008 |
| 7436203 | On-chip transformer arrangement An integrated circuit requires on-chip termination resistor for minimizing reflections from input signals supplied by an external signal source. The input signal is applied across two bonding pads which serve as input terminals for the integrated circuit. The first ... | 10/14/2008 |
| 7434192 | Techniques for optimizing design of a hard intellectual property block for data transmission Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes su... | 10/07/2008 |
| 7432730 | Time based driver output transition (slew) rate compensation Apparatus and method for controlling the driver output slew rate. The apparatus includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A ... | 10/07/2008 |
| 7423451 | System-on-a-chip integrated circuit including dual-function analog and digital inputs An integrated circuit includes a plurality of inputs, a plurality of output pads, a programmable logic block, an analog circuit block, an analog-to-digital converter programmably coupleable to individual analog circuits in the analog circuit block, and an interconne... | 09/09/2008 |
| 7412221 | Crosstalk reduction method, apparatus, and system A data driver drives a data signal on a channel, and a current mode driver drives a varying current on the channel to reduce crosstalk. ... | 08/12/2008 |
| 7411414 | Single-ended output driver buffer Circuits and related methods are provided for buffering reference voltages from noise associated with output driver transistors. In one example, an output driver buffer circuit includes an output driver transistor adapted to adjust an output voltage of an output pad... | 08/12/2008 |
| 7411422 | Driver/equalizer with compensation for equalization non-idealities A high speed serial data communication system includes provisions for the correction of equalization errors, particularly those errors introduced by equalizer non-idealities. The equalization is achieved at the data transmitter, and is based on dynamic current subtr... | 08/12/2008 |
| 7409659 | System and method for suppressing crosstalk glitch in digital circuits A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net, and the net is examined if crosstalk glitch induced in the selected victim net is sufficiently suppressed.... | 08/05/2008 |
