Celebrity Inventors
Mark Twain (Samuel L. Clemens) received Patent No. 121,992 for "An Improvement in Adjustable and Detachable Straps for Garments." He later received two more patents: one for a self-pasting scrapbook and one for a game to help players remember important historical dates.
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| Number | Title | Issue Date |
| 8164357 | Digital noise protection circuit and method A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a ... | 04/24/2012 |
| 7474117 | Bi-directional universal serial bus booster circuit A method of transmitting a signal on a bi-directional universal serial bus (“USB”) circuit for boosting a signal on a USB bus disclosed. The circuit includes a first stage inverting buffer coupled to a second stage inverting buffer to form a non-inverting buffer... | 01/06/2009 |
| 7436214 | Pseudo differential current mode receiver A pseudo differential current mode receiver includes a regulated cascode buffer for buffering a received data current to generate a buffered data current with cascode-reduced input impedance and cascode-increased output impedance. In addition, a signal converter gen... | 10/14/2008 |
| 7409659 | System and method for suppressing crosstalk glitch in digital circuits A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net, and the net is examined if crosstalk glitch induced in the selected victim net is sufficiently suppressed.... | 08/05/2008 |
| 7394281 | Bi-directional universal serial bus booster circuit A bi-directional universal serial bus (“USB”) circuit for boosting a signal on a USB bus disclosed. The circuit includes a first stage inverting buffer coupled to a second stage inverting buffer to form a non-inverting buffer circuit. A high pass filter is coupl... | 07/01/2008 |
| 7365586 | Hysteresis-type input circuit Hysteresis circuit 10 is composed of three inverters 40, 42, 44. Node NB in hysteresis circuit 10 is connected to the input terminal of transition-detecting part 14 of transmission control part 12. Transition-detecting p... | 04/29/2008 |
| 7339396 | Method and apparatus for ameliorating the effects of noise generated by a bus interface A method and apparatus for ameliorating the effects of noise generated by a bus interface provides improved performance of integrated circuits having other circuits sensitive to the transient noise introduced by bus signal switching. Additional signals are generated... | 03/04/2008 |
| 7332930 | Noise canceller circuit A noise canceller circuit capable of suppressing power supply noise, produced by transition of a data signal, even in case a data signal is increased in speed. The noise canceller circuit includes an output buffer 20 for outputting a first binary signal that ... | 02/19/2008 |
| 7323907 | Pre-emphasis driver control Embodiments for controlling pre-emphasis driver circuits for electrical signal interconnects within a computer system are disclosed. ... | 01/29/2008 |
| 7315182 | Circuit to observe internal clock and control signals in a receiver with integrated termination and common mode control A serial data receiver circuit includes a pair of differential input nodes, and receiver circuitry and a termination circuit coupled between the differential input nodes. The termination circuit comprises a common mode node. A common mode control circuit is connecte... | 01/01/2008 |
| 7233164 | Offset cancellation in a multi-level signaling system A receive circuit having a sampling circuit and a threshold generating circuit. The sampling circuit generates a first sample value having either a first state or a second state according whether an incoming signal exceeds a first threshold level, the first threshol... | 06/19/2007 |
| 7218135 | Method and apparatus for reducing noise in a dynamic manner An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indic... | 05/15/2007 |
| 7187227 | Driver circuit A driver circuit includes first and second three-terminal active elements, and first and second delay units. The first and second three-terminal active elements are series-connected. Each of the first and second three-terminal active elements has an amplification fu... | 03/06/2007 |
| 7180325 | Data input buffer in semiconductor device A data input buffer for use in a semiconductor device, including: a detection unit for receiving a reference voltage signal and an input data signal through a first input terminal and a second input terminal respectively in order to detect a voltage level of the inp... | 02/20/2007 |
| 7170312 | Systems and methods for reducing timing variations by adjusting buffer drivability Systems and methods for reducing variations in the timing of signal transitions which may result from interference with neighboring signal lines by adjusting the drivability of in-line buffers based upon the hostile/friendly condition of the neighboring lines. In on... | 01/30/2007 |
| 7143381 | Resonance reduction arrangements Resonance reduction arrangements to reduce the impact of power supply resonance on circuits, comprising a resonance sensor and a charge dumper, wherein upon the detection of the predetermined resonance by the resonance sensor at a circuit location, the charge dumper... | 11/28/2006 |
| 7120408 | Differential signal squelch detection circuit and method An electrical circuit detects a “squelch,” or “out-of-band,” state of a differential signal pair having a positive (“p”) signal line and a negative (“n”) signal line. In one embodiment of the invention, a first and a second comparator each have posit... | 10/10/2006 |
| 7116126 | Intelligent delay insertion based on transition A method of transmitting adjacent signals is disclosed. Sensing is performed on signals in the group and adjacent signals are either switched or delayed if the adjacent signals are switching at the same time. The method is used in networks where coupling and capacit... | 10/03/2006 |
| 7102421 | Dynamically adjustable on-chip supply voltage generation A voltage regulation scheme for an on-chip voltage generator includes a voltage sensing circuit (VSC) and a configurable buffer circuit (CBC) to regulate the on-chip voltage generator. The CBC generates an output signal that is received by the on-chip voltage genera... | 09/05/2006 |
| 7091741 | Input buffer capable of reducing input capacitance seen by input signal Provided is an input buffer whose input capacitance presented to input signals can be reduced. The input buffer includes a first differential amplifier which compares the sizes of a first input signal and a second input signal and outputs an output signal as the res... | 08/15/2006 |
| 6925559 | Reducing effects of transmission line reflections by changing transmission line pedestal voltage or recever threshold voltage while monitoring for irregular synchronization A system and method of reducing an effect of signal distortion from reflection on a transmission line include changing at least one of a pedestal voltage level on the transmission line and a signal threshold voltage level in a processor coupled to the transmission l... | 08/02/2005 |
| 6876224 | Method and apparatus for high speed bus having adjustable, symmetrical, edge-rate controlled, waveforms A method of enhancing noise margin on digital signal lines of a system includes steps of evaluating impedances and lengths of the digital signal lines. Resonances of each digital signal line are determined, and target waveforms for each digital signal line optimized... | 04/05/2005 |
| 6873178 | Skewed bus driving method and circuit Circuits and methods for driving buses (data buses or address buses) which provide a reduction in interference such as crosstalk between adjacent bus lines of a bus, even as the width of the bus increases and the intervals between the bus lines decrease. In the bus ... | 03/29/2005 |
| 6870389 | Differential circuit with current overshoot suppression A differential driver circuit that suppresses current overshoot and allows current switching to proceed at near the maximum speed includes: a differential pair Q5 and Q6 having a tail current source I56; a first buffer Q3 providing a firs... | 03/22/2005 |
| 6842044 | Glitch-free receivers for bi-directional, simultaneous data bus A structure and method for eliminating glitches at the output of a receiver receiving signals sent to one end of a bi-directional, simultaneous transmission line. The receiver comprises two comparators, a logic circuit, a glitch detector, and a programmable delay un... | 01/11/2005 |
| 6794893 | Pad circuit and method for automatically adjusting gain for the same A pad circuit and operating method for automatically adjusting gains is disclosed, wherein the pad circuit is embedded in an integrated circuit chip that further includes a core logic circuit therein. The pad circuit includes an input/output pin, a gain-adjustable o... | 09/21/2004 |
| 6703869 | Method and apparatus for low latency distribution of logic signals A series of logic clouds is used to distribute and propagate signals traveling a relatively long distance across a data logic circuit fabric. One or more long distance signals originate from an initial logic cloud that may be located on a source data bloc... | 03/09/2004 |
| 6675331 | Testable transparent latch and method for testing logic circuitry that includes a testable transparent latch A transparent latch (18) and a logic conditioning circuit (10) are disclosed. The transparent latch (18) receives signals from conditioning circuit (10), including a test input that indicates whether the transparent latch is in a testing mode or an operat... | 01/06/2004 |
| 6661255 | Interface circuit An interface circuit for a printer to prevent transmission of an incorrect control signal when power is input into the printer. The interface circuit improves the stability of the printer at the initial state of the rise of power supply voltages, and prev... | 12/09/2003 |
| 6563344 | Buffer circuit for the reception of a clock signal A buffer circuit includes an input for receiving a logic signal, and a transfer circuit for transferring the logic signal from the input to an output of the buffer circuit. The transfer circuit includes at least one logic gate having a trip point sensitiv... | 05/13/2003 |
| 6549033 | Signal processing device and process and electrical apparatus comprising such a device The signal processing device comprises determining means to supply an output signal having a value representative of a time constant of a part of an input signal having an appreciably exponential form. The determining means comprise first integrating mean... | 04/15/2003 |
| 6542003 | Circuit configuration and method for directly electrically isolated broadband transmission In order to enable a simple and cost-effective directly electrically isolated transmission of data signals, the data signals are superposed on a clock signal in an input stage and are transmitted to an output stage in a directly electrically isolated mann... | 04/01/2003 |
| 6538473 | High speed digital signal buffer and method One embodiment of a complimentary input buffer uses six symmetrically arranged inverters. A pair of inverters are coupled between a respective input terminal and a respective output terminal with the input of the inverters coupled to the input terminals a... | 03/25/2003 |
| 6515512 | Capacitively coupled re-referencing circuit with transient correction A re-referencing circuit for re-referencing a digital input signal from a first logic environment to a second logic environment includes a non-inverting circuit having a non-inverting transfer characteristic between the input and the output. A capacitive ... | 02/04/2003 |
| 6476640 | Method for buffering an input signal A buffer having first and second input terminals and an output terminal. The buffer also includes a fast edge driver having an input terminal and an output terminal, with the input terminal connected to the first input terminal of the buffer, and the outp... | 11/05/2002 |
| 6429690 | Programmable linear transconductor circuit A programmable linear transconductor circuit is disclosed. The programmable linear transconductor circuit includes a first current source and a second current source, a first group of transistors and a second group of transistors, a first load coupled to ... | 08/06/2002 |
| 6351158 | Floating gate circuit for backwards driven MOS output driver A bus driver circuit has floating gate circuits with three transistors. Two of the transistors for an inverter for operating the output power transistor. The third transistor is connected to receive control signals from well pull circuits. The control sig... | 02/26/2002 |
| 6184717 | Digital signal transmitter and receiver using source based reference logic levels A signal transmitter for transmitting digital logic signals and a complementary receiver, are disclosed. The signal transmitter comprises a plurality of signal drivers and at least one reference driver. The signal drivers transmit digital signals, while t... | 02/06/2001 |
| 6137306 | Input buffer having adjustment function for suppressing skew An input buffer of the present invention includes: a plurality of receiver circuits for performing different phase adjustments on an input signal, and outputting the differently phase-adjusted signals; a pattern detection circuit for detecting a period of... | 10/24/2000 |
| 6094062 | Coupled noise reduction circuitry Switching on a first line, from a first signal level to a second level, tends to induce a change in signal level of a second line. To reduce induced noise, the second line is connected to a power rail for a predetermined time interval, responsive to the s... | 07/25/2000 |
