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| Number | Title | Issue Date |
| 8143911 | Input/output driver swing control and supply noise rejection In general, in one aspect, the disclosure describes an apparatus having an averager to receive differential output voltages of a transmitter and generate an average transmitter output voltage. A comparator is to compare the average transmitter output voltage to a re... | 03/27/2012 |
| 8125240 | Multichannel interfacing device having a balancing circuit The invention relates to an interfacing device for transmission through interconnections used for sending a plurality of electrical signals. The interfacing device of the invention comprises signal terminals and a common terminal. A transmitting circuit recei... | 02/28/2012 |
| 8098079 | Receive circuit for connectors with variable complex impedance Embodiments of a circuit for use with an inter-chip connection that has a variable complex impedance (which can be conductive, capacitive or both), a system that includes the circuit, and a communication technique are described. This inter-chip connection may be for... | 01/17/2012 |
| 8067955 | Preventing erroneous operation in a system where synchronized operation is required This invention is a method of operating a system having multiple finite state machines where each finite state machine generating a ready signal when its operation is complete. This invention senses the multiple ready signals and waits until all the finite state mac... | 11/29/2011 |
| 8013628 | Circuit having an active clock shielding structure and semiconductor intergrated circuit including the same A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep ... | 09/06/2011 |
| 8004307 | Static-dynamic-dynamic repeater circuit A repeater circuit. The repeater circuit includes two input circuits, two intermediate circuits, and two output circuits. Responsive to a transition of an input signal from one logic level to another level, one of the input circuits is activated. The corresponding i... | 08/23/2011 |
| 7986159 | Method and apparatus for detecting a cable in a redriver With conventional redrivers used for external Serial Advanced Technology Attachment (eSATA), there is no ability to indicated to a host that an external device (like a hard disk drive) is not present. As a result, power is consumed by a host because of nearly contin... | 07/26/2011 |
| 7952380 | Pseudo-differential interfacing device having a balancing circuit The invention relates to an interfacing device for pseudo-differential transmission through interconnections used for sending a plurality of electrical signals. The interfacing device of the invention includes signal terminals and a common terminal. A transmitting c... | 05/31/2011 |
| 7944231 | Electronic device for the transport of numerical information An electronic device designed to transport digital information (“0”, “1”) over long distances, including a transmitter generating current pulses and at least one assembly of receivers converting the received current pulses into logic pulses which are compati... | 05/17/2011 |
| 7940074 | Data transmission circuit and semiconductor apparatus including the same A data transmission circuit includes a data transmission unit and a data receiving unit. The data transmission unit generates transmission data based on first chip data and transmit the transmission data via a Through Silicon Via (TSV). The data receiving unit diffe... | 05/10/2011 |
| 7911222 | Mix mode driver for traces of different lengths A method for a mix mode driver to accommodate traces of different lengths includes storing in the mix mode driver a set of one or more control signals and coefficient signals for a trace length. The one or more control signals select a number of the stages to genera... | 03/22/2011 |
| 7884636 | Single event transient mitigation and measurement in integrated circuits A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate... | 02/08/2011 |
| 7859294 | Method and arrangement for reducing power in bidirectional input/output ports An arrangement and method of reducing power in bidirectional I/O ports includes driving an input signal from an I/O port by asserting a high impedance (Hi-Z) signal to an output drive, driving an output signal from the I/O port by refraining from asserting a Hi-Z si... | 12/28/2010 |
| 7839161 | Low-jitter high-frequency clock channel According to one general aspect, an apparatus may include a clock channel, a shielding tunnel, and clock repeaters. In various embodiments, the clock channel may be configured to carry the clock signal, and may include a portion of a metal layer of an integrated cir... | 11/23/2010 |
| 7830166 | Pulse shift modulation for reducing cross-talk of single ended I/O interconnects A method and apparatus is described herein for pulse shift modulation of output waveforms for reducing crosstalk on interconnects. Based on input pulses/bits, an output waveform is selectively delayed by a shift value to ensure transitions in a first direction occur... | 11/09/2010 |
| 7812631 | Sleep transistor array apparatus and method with leakage control circuitry In some embodiments, an array of sleep transistors is provided, wherein a combination of said transistors may be enabled during an active mode to reduce leakage depending on the leakage characteristics of a chip or associated chip. ... | 10/12/2010 |
| 7772874 | Single event transient mitigation and measurement in integrated circuits A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate... | 08/10/2010 |
| 7755381 | Reducing noise on a supply voltage in an integrated circuit An IC uses a tunable interconnect driver between a data source and a data destination to selectively slow down (“de-tune”) data signals. Data sent along relatively short paths are de-tuned to reduce power supply noise during synchronous switching events. In some... | 07/13/2010 |
| 7746095 | Memory module and method having improved signal routing topology A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends ... | 06/29/2010 |
| 7719305 | Signal isolator using micro-transformers A logic signal isolator including a micro-transformer with a primary winding and a secondary winding. A transmitter circuit drives the primary winding in response to a received input logic signal such that, in response to a first type of edge in the logic signal, at... | 05/18/2010 |
| 7692444 | Signal isolators using micro-transformers A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a si... | 04/06/2010 |
| 7683655 | Integrated circuit An integrated circuit is provided having at least one terminal for coupling and/or decoupling of electric signals, particularly of digital signals, and having integrated reference potential means, assigned to the terminal, for providing an electric reference potenti... | 03/23/2010 |
| 7683654 | Signal isolators using micro-transformers A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a si... | 03/23/2010 |
| 7683656 | Predriver equalization for common mode noise reduction in a semi-differential current mode driver Predriver equalization is described. A predriver includes a predriver equalizer to provide equalization on outputs of predrivers. The predriver equalization causes the predrivers to drive the output driver and a preemphasis driver with signals equalized to reduce co... | 03/23/2010 |
| 7642807 | Multiple-mode compensated buffer circuit A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. R... | 01/05/2010 |
| 7639037 | Method and system for sizing flow control buffers A system that includes a first buffer and a second buffer, wherein the first buffer and the second buffer are connected to the same input, wherein a size of the first buffer is defined by a distance of the first buffer from the input and a transfer rate of data, whe... | 12/29/2009 |
| 7622945 | Mix mode driver for traces of different lengths A method for a mix mode driver to accommodate traces of different lengths includes sequentially shifting values of a data signal to a number of stages and sequentially amplifying the values of the data signal at least one stage. Depending on the length of trace for ... | 11/24/2009 |
| 7605601 | Semiconductor integrated circuit device A semiconductor integrated circuit device, has a semiconductor substrate; and a first transistor of a first conductivity type and a second transistor of the first conductivity type, the transistors being connected in series between a first power supply line and a fi... | 10/20/2009 |
| 7557601 | Memory module and method having improved signal routing topology A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends ... | 07/07/2009 |
| 7514952 | I/O circuitry for reducing ground bounce and VCC sag in integrated circuit devices Methods and circuitry for reducing ground bounce and VCC sag effects in integrated circuit (“IC”) devices is provided. In particular, a via-programmable design for I/O circuitry in IC devices is provided. The via-programmable I/O circuitry is used to disconnect ... | 04/07/2009 |
| 7439773 | Integrated circuit communication techniques An semiconductor device, containing logic blocks and high speed connections between the blocks, where the connections utilize current direction for logic representation rather than voltage level. Such high speed connections comprise differential transmitters which d... | 10/21/2008 |
| 7432730 | Time based driver output transition (slew) rate compensation Apparatus and method for controlling the driver output slew rate. The apparatus includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A ... | 10/07/2008 |
| 7428465 | Testing control methods for use in current management systems for digital logic devices Systems and methods for Current Management of Digital Logic Devices are provided. In one embodiment a method for calibrating a digital logic circuit current management system is provided. The method comprises activating one or more synchronous logic paths of a plura... | 09/23/2008 |
| 7427872 | Asynchronous coupling and decoupling of chips In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the firs... | 09/23/2008 |
| 7421530 | Noise attenuating bus structure and method for a mobile communication A bus structure of a mobile communication terminal for reducing digital noise is disclosed. The bus structure comprises a bus switch controller, a first element having a first bus, a second element having a second bus, and a common bus for connecting the first bus a... | 09/02/2008 |
| 7411416 | Technology for supressing noise of data bus circuit A data bus circuit connects a south bridge driven by a first voltage and a bay driven by a second voltage. The first voltage and the second voltage are different. The data bus circuit includes a data bus that electrically connects the south bridge and the bay, and a... | 08/12/2008 |
| 7405598 | Differential line compensation apparatus, method and system A differential line compensation apparatus is disclosed that has a first terminal to receive a first differential signal supplied by a first trace and a second terminal to receive a second differential signal supplied by a second trace. The apparatus has at least on... | 07/29/2008 |
| 7405591 | Concept for interfacing a first circuit requiring a first supply voltage and a second supply circuit requiring a second supply voltage An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminal... | 07/29/2008 |
| 7397270 | Dynamically-adjustable differential output drivers Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuit... | 07/08/2008 |
| 7394282 | Dynamic transmission line termination A system may include detection of a low signal received from a transmission line, and uncoupling of a termination circuit from the transmission line in response to the detected low signal. In some aspects, a transition of a strobe signal is then detected, and the te... | 07/01/2008 |
