Did You Know...
...that the Eveready Battery began as an invention called the "electric flowerpot," which was a tube with a battery and light bulb inside? The idea was to fasten this gizmo to the side of a flowerpot so it would illuminate the flowers from the bottom. The idea died on the vine and the businessman who licensed the flower pot, Conrad Huber, was left with a pile of useless tubes -- until he found a way to market them as batteries to light the world!
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| Number | Title | Issue Date |
| 7498833 | Semiconductor integrated circuit A semiconductor integrated circuit comprises logic cones having a structure in which substrates thereof are isolated from each other and substrate potentials can be controlled, and a potential switching section for supplying a substrate voltage from any of a first s... | 03/03/2009 |
| 7397271 | Semiconductor integrated circuit device A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells has: a standard cell which includes a MIS transistor, the standard cell including an input terminal t... | 07/08/2008 |
| 7372319 | Constant boosted voltage generator circuit for feedback switches in a switched capacitor circuit A boosted voltage generator circuit includes a precharge voltage generator circuit and a first capacitor. The precharge voltage generator circuit receives a first DC voltage and a first power supply voltage and generates a precharge voltage having a first voltage va... | 05/13/2008 |
| 7336104 | Multiple-output transistor logic circuit A logic circuit consists of a first transistor network and a complementary second transistor network connected at a central node. The central node serves as a first logic output. Each of the transistor networks is also connected to a respective root. A third transis... | 02/26/2008 |
| 7336105 | Dual gate transistor keeper dynamic logic A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its inp... | 02/26/2008 |
| 7336101 | Control circuit and method A control circuit including a first control unit, controlling a logic circuit, connected between a power supply and a virtual ground, the control unit connecting the virtual ground to a ground in response to a mode control signal when the logic circuit operates in a... | 02/26/2008 |
| 7319342 | Data acceleration device and data transmission apparatus using the same A data acceleration device may include a pull-up driver for driving a pull-up in response to the signal level on a first node, a pull-down driver for driving a pull-down in response to the signal level on the first node, a first pull-up circuit for pull-up driving a... | 01/15/2008 |
| 7304503 | Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability, is provided and described. In one embodiment, switches are set to a first switch position to operate the repeater circuit... | 12/04/2007 |
| 7287235 | Method of simplifying a circuit for equivalence checking A method of simplifying a logic circuit for enabling cycle-by-cycle equivalence checking is provided. To accomplish this, first, a logic circuit is identified to be a variable delay circuit or a fixed delay circuit. If the logic circuit is a variable delay circuit, ... | 10/23/2007 |
| 7282981 | Level conversion circuit with improved margin of level shift operation and level shifting delays To provide a level shift circuit in which the margin of level shift operation is prevented from deteriorating when the potential difference between a first power supply and a second power supply is large. A level shift circuit for changing the signal level in a firs... | 10/16/2007 |
| 7256624 | Combined output driver A combined output driver for TMDS signals and LVDS signals. First and second output drivers output first and second differential signals to a first external input unit and a second external input unit, respectively, through a pair of signal lines according to first ... | 08/14/2007 |
| 7239185 | Driver circuit connected to pulse shaping circuitry An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PF... | 07/03/2007 |
| 7236045 | Bias generator for body bias A bias generator is provided that includes a central bias generator to provide a first bias voltage and a local bias generator to receive the first bias voltage and to provide a second bias voltage. The central bias generator may include a replica bias generator cir... | 06/26/2007 |
| 7224201 | Level converter The invention relates to a level converter for converting a signal (in) comprising a first voltage level (Vint) and supplied to the level converter, to a signal (Out) including a second voltage level (Vsupply) differing from the first voltage level (Vint). The level... | 05/29/2007 |
| 7221605 | Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorb... | 05/22/2007 |
| 7212030 | Field programmable gate array long line routing network A multi-directional routing repeater has a plurality of buffers, each of the plurality of buffers has an input and an output. The output of each of the plurality of buffers is connected to a separate routing line for transmitting a signal in a separate direction of ... | 05/01/2007 |
| 7212029 | Circuit arrangement for the operation of a switching transistor The circuit arrangement comprises a driver stage and a control circuit coupled to the control input of a switching transistor. The driver stage provides a switching voltage for the operation of the switching transistor, and the control circuit provides a shaping of ... | 05/01/2007 |
| 7202725 | Delay control circuit device, and a semiconductor integrated circuit device and a delay control method using said delay control circuit device By forming adjacent wiring 4 adjacent to signal wiring 3 and using a control circuit 13 comprising a 2-input NAND 20 circuit or the like to input a signal S4 corresponding to a signal S3 in the signal wiring 3 to the ... | 04/10/2007 |
| 7183806 | Output circuit Since voltages of two input terminals of an output unit having an online download function are decided by voltages which are not correlative to each other, a value of an incoming current on the start-up becomes large. The present invention solves the problem of turn... | 02/27/2007 |
| 7177349 | High impedance state for digital subscriber line transceivers on copper twisted pairs The invention relates to methods and a high speed communication device that allow one of a plurality of high speed communication devices connected to a transmission line having a normal impedance to effectively receive data. The high speed communication devic... | 02/13/2007 |
| 7154293 | High-speed transmitter circuit A signal for the single-wire circuit is inputted and separated into two signals by the input separator circuit and the two signals are inputted in parallel into the two-wire transmitter circuit comprises at least one set of logic gates in which a P-channel CMOS tran... | 12/26/2006 |
| 7142018 | Circuits and methods for detecting and assisting wire transitions A circuit for assisting signal transitions on a wire, and a method thereof. The circuit includes a first subcircuit that causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and then turn off. The first transistor d... | 11/28/2006 |
| 7098684 | High speed switch A high speed switch. The novel switch includes an input circuit having a transistor Q1 for receiving an input signal, a first mechanism for providing a path from an output of Q1 to an output terminal, and a second mechanism for receiving a control sign... | 08/29/2006 |
| 7084666 | Programmable interconnect structures A programmable interconnect structure in an integrated circuit comprising: a plurality of wires; and a buffer comprising an input and an output, said buffer receiving a weak signal at the input and providing a buffered signal at the output; and a first programmable ... | 08/01/2006 |
| 7068067 | Semiconductor circuit device having active and standby states A P channel MOS transistor and an N channel MOS transistor turned on/off in response to an input signal in an active state as well as an N channel MOS transistor connected between an output node and the N channel MOS transistor and turned on/off in response to a con... | 06/27/2006 |
| 7064584 | P-domino output latch with accelerated evaluate path An apparatus and method are provided for accelerating the evaluated output of an P-domino latch. The apparatus includes evaluation P-logic, latching logic, keeper logic, and acceleration logic. The evaluation P-logic is coupled to a first N-channel device at a pre-c... | 06/20/2006 |
| 7053651 | Low power CMOS switching A CMOS switching circuit that includes a charge reservoir and a multiplexer connected to the charge reservoir. The multiplexer receives control signals from a delay line and a control signal line, and it delivers a switching signal to an output terminal. A first set... | 05/30/2006 |
| 7042266 | Delay circuit and method A delay circuit does not lead to excessive increase in the delay time even if the source voltage drops, and enables to control the delay time from increasing. The delay circuit is designed to delay a logic signal SIN having two logic levels consisting of a low level... | 05/09/2006 |
| 7034578 | N-domino output latch with accelerated evaluate path An apparatus and method are provided for accelerating the evaluated output of an N-domino latch. The apparatus includes evaluation N-logic, latching logic, keeper logic, and acceleration logic. The evaluation N-logic is coupled to a first P-channel device at a pre-c... | 04/25/2006 |
| 7030673 | Phase splitter circuit A phase splitter circuit includes a first signal generator and a second signal generator. The first signal generator generates a first signal in response to an input signal. The second signal generator generates a second signal in response to the input signal. The p... | 04/18/2006 |
| 7005892 | Circuit technique for high speed low power data transfer bus A high speed low power data transfer bus circuit that reduces bus power consumption by imposing a limited, controlled voltage swing on the associated data bus. In one embodiment, an inverter is coupled with a pMOS pass transistor and an nMOS discharge transistor, an... | 02/28/2006 |
| 6996652 | High-speed segmented data bus architecture A system is provided for driving data signals in an integrated circuit device. The system includes a plurality of functional blocks, each having at least one input/output connection along one side of the integrated circuit device. A data bus comprises a plurality of... | 02/07/2006 |
| 6956398 | Leakage current reduction method The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power s... | 10/18/2005 |
| 6952113 | Method of reducing leakage current in sub one volt SOI circuits A multi-threshold integrated circuit (IC) with reduced subthreshold leakage and method of reducing leakage. Selectable supply switching devices (NFETs and/or PFETs) between a logic circuit and supply connections (Vdd and Ground) for the circuit have highe... | 10/04/2005 |
| 6949948 | Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates... | 09/27/2005 |
| 6940332 | Level shift circuit having control circuits for high speed, area saving and power saving A level shift circuit realizes a high-speed and power-saved operation particularly when the input voltage is at a low level. The level shift circuit includes a first gate voltage control circuit controlled by an inverted signal of an input signal, which is inserted ... | 09/06/2005 |
| 6937080 | Current-controlled CMOS logic family Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, X... | 08/30/2005 |
| 6933744 | Low-leakage integrated circuits and dynamic logic circuits An integrated circuit is disclosed that includes one or more blocks of switching logic (comprised of transistors) connected between a power supply and a common node. A control transistor connects the common node to ground. The control transistor has a higher thresho... | 08/23/2005 |
| 6928506 | Apparatus using bus capacitance to perform data storage during data transfer across the bus The invention relates to a circuit arrangement with two or more circuit sections, which cooperate through a data transfer device. The invention solves the problem of double area expenditure for two memory devices for each receiver, in that the data bus itself takes ... | 08/09/2005 |
| 6914449 | Structure for reducing leakage current in submicron IC devices A technique for reducing leakage current in static CMOS devices by adding additional transistors in series between selected inverters or logic gates and ground or power. NMOS and PMOS transistors are added to selected buffers comprised of two inverters in series. Th... | 07/05/2005 |
