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Pet Toilet-Like Water Disk and Food Storage
One pet-friendly inventor patented "a device for watering pets, e.g., a dog or cat." The device, he helpfully noted, "has the general shape of a toilet."
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| Number | Title | Issue Date |
| 8130009 | Dynamic voltage and frequency management In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the t... | 03/06/2012 |
| 8072234 | Micro-granular delay testing of configurable ICs A method for testing a set of circuitry in an integrated circuit (IC) is described. The IC includes multiple configurable circuits for configurably performing multiple operations. The method configures the IC to operate in a user mode with a set of test paths that s... | 12/06/2011 |
| 8035411 | Semiconductor integrated circuit including a power controllable region Provided is a semiconductor integrated circuit capable of testing power control operation in the semiconductor integrated circuit including a power controllable region. Power control switches have switch series each constituted by a plurality of switch cells. A powe... | 10/11/2011 |
| 8026737 | Fusing apparatus for correcting process variation An fusing apparatus for correcting process variation is provided. The fusing apparatus for correcting the process variation of the semiconductor device includes a fusing part including a fusing resistor fused by a current penetrating; a current driving transistor fo... | 09/27/2011 |
| 8008943 | Semiconductor device A semiconductor device includes a plurality of pads configured to receive a plurality of external signals, an internal circuit configured to perform a predetermined internal operation in response to one of the external signals that is inputted through one of the plu... | 08/30/2011 |
| 7977967 | Method for solid state thermal electric logic A method is provided for thermal electric binary logic control. The method accepts an input voltage representing an input logic state. A heat reference is controlled in response to the input voltage. The method supplies an output voltage representing an output logic... | 07/12/2011 |
| 7977966 | Internal voltage generating circuit for preventing voltage drop of internal voltage An internal voltage generating circuit is utilized to perform a TDBI (Test During Burn-in) operation for a semiconductor device. The internal voltage generating circuit produces an internal voltage at a high voltage level, as an internal voltage, in not only a stand... | 07/12/2011 |
| 7969180 | Semiconductor integrated circuit A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first ... | 06/28/2011 |
| 7936179 | Semiconductor integrated circuit and method of testing circuit A semiconductor integrated circuit includes: a ladder resistor; a ROM decoder; and a test circuit. The ladder resistor includes a plurality of resistors series-connected to each other and is supplied with a correction voltage at least one of both ends of the series ... | 05/03/2011 |
| 7919977 | Circuits and methods for testing FPGA routing switches An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at leas... | 04/05/2011 |
| 7915910 | Dynamic voltage and frequency management In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the t... | 03/29/2011 |
| 7911221 | Semiconductor device with speed performance measurement A speed performance measurement circuit that may perform speed performance measurement is provided between a first logic circuit and a second logic circuit. The speed performance measurement circuit includes a first flip flop that stores first data, a first delay ci... | 03/22/2011 |
| 7898285 | Optimal local supply voltage determination circuit A test circuit that compares test results between two tests with different local supply voltages is provided. The output of each stage of the logic circuits is stored in a first register of each test circuit. Each test is performed with a critical test vector and a ... | 03/01/2011 |
| 7898286 | Critical path redundant logic for mitigation of hardware across chip variation Cross-die connection structure and method for a die or chip includes buffer elements having a buffer driver and bypass, and control lines coupled to the buffer elements in order to select one of the buffer driver and bypass for each respective buffer element. A logi... | 03/01/2011 |
| 7884635 | Integrated circuit, system and method including a performance test mode An integrated circuit includes N configurable cells each including one functional input, one output, one propagation input and one output. The circuit includes a functional mode in which the N configurable cells are coupled by their functional input and their output... | 02/08/2011 |
| 7872490 | Semiconductor integrated circuit and method for testing the same A semiconductor integrated circuit includes a plurality of clock gating circuits, a plurality of flip-flops to which transmission of a clock signal is controlled by a respective clock gating circuit, and a clock gating control circuit that controls an active state a... | 01/18/2011 |
| 7868647 | Semiconductor device A semiconductor device includes a plurality of pads configured to receive a plurality of external signals, an internal circuit configured to perform a predetermined internal operation in response to one of the external signals that is inputted through one of the plu... | 01/11/2011 |
| 7859293 | Semiconductor integrated circuit A semiconductor integrated circuit includes a digital circuit and a first-stage register circuit provided in a stage followed by the digital circuit. The digital circuit includes a logic circuit and a register circuit configured to temporarily retain a logic output ... | 12/28/2010 |
| 7852109 | Method and apparatus for supplying a clock to a device under test A method and apparatus involves operating a circuit having a test circuit interrupt input terminal (INTERRUPT), having a test circuit clock output terminal (DUT_CLK), and having first and second operational modes. In the first operational mode the circuit supplies a... | 12/14/2010 |
| 7847582 | Logic circuit including a plurality of master-slave flip-flop circuits According to an aspect of an embodiment, a logic circuit includes a first master latch included in one of the master-slave flip-flop circuits, the first master latch having a first scan data input for receiving scan data, the first master latch latching the scan dat... | 12/07/2010 |
| 7843210 | Semiconductor integrated circuit device and testing method of the same A disclosed semiconductor integrated circuit device includes a logic circuit, a memory circuit to which data are written by the logic circuit and from which the data are read by the logic circuit, a register circuit holding the data when the logic circuit writes the... | 11/30/2010 |
| 7804321 | Circuits and methods for testing FPGA routing switches An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at leas... | 09/28/2010 |
| 7795901 | Automatic isolation of a defect in a programmable logic device A defect is automatically isolated in an integrated circuit device having programmable logic and interconnect circuits. A sequence of configurations is created to route data in a pattern through the programmable logic and interconnect circuits. Each configuration wi... | 09/14/2010 |
| 7786749 | Programmable integrated circuit having built in test circuit A programmable integrated circuit has a plurality of logic elements with each logic element having a plurality of input leads and at least one output lead. The programmable integrated circuit further comprises a group of interconnect lines, and a first set of progra... | 08/31/2010 |
| 7772873 | Solid state thermal electric logic A method is provided for thermal electric binary logic control. The method accepts an input voltage representing an input logic state. A heat reference is controlled in response to the input voltage. The method supplies an output voltage representing an output logic... | 08/10/2010 |
| 7768294 | Pulse latch circuit and semiconductor integrated circuit The disclosed invention is intended to decrease the power consumption of a pulse latch circuit. A pulse latch circuit that operates in sync with a pulsed clock signal, including a first operation mode in which shifting test pattern scan data is performed and a secon... | 08/03/2010 |
| 7750665 | Semiconductor device A semiconductor device according to the present invention includes an internal circuit executing a predetermined processing based on signal input from an external device, an output buffer driving line connected to an output terminal based on signal output from the i... | 07/06/2010 |
| 7728617 | Debug network for a configurable IC Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits grouped in several tiles. The configurable IC also includes a configuration network for loading configuration data into the IC, where the con... | 06/01/2010 |
| 7724023 | Circuit apparatus including removable bond pad extension Embodiments of the invention include an electrical circuit arrangement including a switchably removable bond pad extension test pad that allows improved testing of a corresponding electrical circuit device via enhanced placement of testing probes. The bond pad exten... | 05/25/2010 |
| 7724024 | Semiconductor device with its test time reduced and a test method therefor In a semiconductor device, when a voltage regulator is halted from operating and a test supply voltage is supplied to second logics, the device is initialized by a reset signal. A register included in the device is then reset by an input signal via first logics. The... | 05/25/2010 |
| 7688103 | Cell with fixed output voltage for integrated circuit The invention relates to a testable integrated circuit. In order to replace ground and VDD in certain points of such a circuit, the circuit comprises a cell (34) which comprises a flipflop (11) and means (31) able to set the output voltage of th... | 03/30/2010 |
| 7683653 | Process and circuit for improving the life duration of field-effect transistors The invention concerns a process and a circuit designed to improve the life duration of electronic field-effect integrated circuit transistors and in particular those with a thin film gate dielectric. According to the invention, an aging measurement tS | 03/23/2010 |
| 7649379 | Reducing mission signal output delay in IC having mission and test modes An integrated circuit apparatus includes a switching circuit that provides respective signal paths to permit a mission signal, a test signal, and a boundary scan test signal to share an output terminal. The signal path associated with the mission signal imposes a sm... | 01/19/2010 |
| 7646210 | Method and system for low-power level-sensitive scan design latch with power-gated logic A method of preventing current leakage in logic circuits within level sensitive scan design (LSSD) latch circuits in an application specific integrated circuit (ASIC). When the ASIC is in a manufacturing test mode, a gating signal at an input terminal of a power gat... | 01/12/2010 |
| 7639036 | Semiconductor integrated circuit A semiconductor integrated circuit having a test circuit for inspecting states of connections between a plurality of pads and respective external terminals by bonding wires. The test circuit comprises, for each of a plurality of pads, a control terminal provided to ... | 12/29/2009 |
| 7629810 | Input and output circuit Stable testing is performed on an input and output circuit. An output stage outputting output signal to input/output terminal DQ comprises: a differential pair formed from an Nch transistor N1, having as load a Pch transistor P1 and resistance element ... | 12/08/2009 |
| 7595655 | Retrieving data from a configurable IC Some embodiments provide a configurable integrated circuit (IC). The IC has configurable logic circuits for performing logical operations, configurable routing circuits for routing signals between the configurable logic circuits, and a network for monitoring data. I... | 09/29/2009 |
| 7570076 | Segmented programmable capacitor array for improved density and reduced leakage A capacitor circuit and method to reduce layout area, leakage current, and to improve yield is disclosed. The circuit includes an output terminal (100), a plurality of circuit elements (322, 326, 330), and a plurality of transistors (320, 324, 328 | 08/04/2009 |
| 7548085 | Random access of user design states in a configurable IC Some embodiments of the invention is a configurable integrated circuit (IC) that includes (1) several configurable logic circuits, (2) a first routing network for connecting the configurable logic circuits, (3) several user design state (UDS) circuits, and (4) a sec... | 06/16/2009 |
| 7518394 | Process monitor vehicle A method and apparatus is provided for the implementation of a process monitor vehicle (PMV) for memory cells. The memory cell PMV is useful in characterizing drive strength of the N-type and P-type field effect transistors (FETs) that are used to implement the memo... | 04/14/2009 |
