Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
PatentStorm News
Make the Most of PatentStorm
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest patents by subscribing to an RSS feed.
Got questions? Ask a Patent Expert!
Registered users: Manage your profile, comments and alerts.
| Number | Title | Issue Date |
| 7675314 | Receiver circuit In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predet... | 03/09/2010 |
| 7656185 | Semiconductor integrated circuit device with a fail-safe IO circuit and electronic device including the same A semiconductor IC device includes at least one IO port, a core logic, and at least one fail-safe IO circuit, the fail-safe IO circuit being coupled between the core logic and the IO port, wherein the fail-safe IO circuit is configured to receive a predetermined con... | 02/02/2010 |
| 7443191 | Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the rou... | 10/28/2008 |
| 7427871 | Fault tolerant integrated circuit architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element inter... | 09/23/2008 |
| 7427872 | Asynchronous coupling and decoupling of chips In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the firs... | 09/23/2008 |
| 7423448 | Radiation hardened logic circuit A radiation-hardened logic circuit prevents SET-induced transient pulses from propagating through the circuit, using two identical logic paths. The outputs of the two logic paths are fed into an exclusive-OR gate, which controls gating circuitry. The gating circuitr... | 09/09/2008 |
| 7424642 | Method for synchronization of a controller A system and method for reintegration of a redundant controller after occurrence of a fault is provided, comprising synchronizing outputs of a primary controller with outputs of secondary controllers. The controller is placed in a different mode of operation in whic... | 09/09/2008 |
| 7397268 | Receiver circuit In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predet... | 07/08/2008 |
| 7397269 | Disconnection and short detecting circuit that can detect disconnection and short of a signal line transmitting a differential clock signal Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal input... | 07/08/2008 |
| 7386826 | Using redundant routing to reduce susceptibility to single event upsets in PLD designs Methods of implementing designs in programmable logic devices (PLDs) to reduce susceptibility to single-event upsets (SEUs) by taking advantage of the fact that most PLD designs leave many routing resources unused. The unused routing resources can be used to provide... | 06/10/2008 |
| 7362558 | Protective device in a controller In the case of a protective device in a controller which contains at least one processor and is connected to a sensor via a sensor ground line and at least one further line, the invention provides that a ground in the controller is connected to the sensor ground lin... | 04/22/2008 |
| 7355437 | Latch-up prevention circuitry for integrated circuits with transistor body biasing An integrated circuit such as a programmable logic device integrated circuit is provided that contains body-biased metal-oxide-semiconductor transistors and latch-up prevention circuitry to prevent latch-up from occurring in metal-oxide-semiconductor transistors. Bo... | 04/08/2008 |
| 7345502 | Design security for configurable devices Methods and structures for design security in configurable devices are described. In some embodiments, a configurable device may be placed in an unsecured mode allowing for access to configuration data and other diagnostic functions during development and production... | 03/18/2008 |
| 7337357 | Apparatus, system, and method for limiting failures in redundant signals An apparatus, system, and method are disclosed for limiting failures in redundant signals. A coordination module generates a power status signal for each of a plurality of power modules. An input module receives a source signal. A signal generation module generates ... | 02/26/2008 |
| 7301362 | Duplicated double checking production rule set for fault-tolerant electronics Systems and methods for mitigating the effects of soft errors in asynchronous digital circuits. Circuits are constructed using stages comprising doubled logic elements which are connected to c-elements that compare the output states of the double logic elements. The... | 11/27/2007 |
| 7295412 | Protection circuit for power management semiconductor devices and power converter having the protection circuit A collector voltage of a power management semiconductor device is detected by a first comparator, and when the detected collector voltage exceeds a first reference voltage, the first comparator outputs a first detection signal. Furthermore, a gate voltage of the pow... | 11/13/2007 |
| 7295044 | Receiver circuits for generating digital clock signals A digital clock generation circuit (and a method for operating the same). The digital clock generation circuit includes a first, a second, a third differential comparator circuits. The first differential comparator circuit receives the positive differential clock si... | 11/13/2007 |
| 7292076 | Low voltage pull-down circuit A low voltage pull-down circuit for maintaining a node at a logic LOW voltage is provided. When a logic LOW is desired, the circuit provides a low-impedance path from the node to ground. The node may be pulled-up to a logic HIGH voltage, for example, by removing the... | 11/06/2007 |
| 7276957 | Floating well circuit having enhanced latch-up performance A circuit for defining a voltage potential of a floating well in which is formed at least one metal-oxide-semiconductor device includes a sense circuit operative to detect a voltage at a node to which the floating well is connected and to generate a control signal i... | 10/02/2007 |
| 7265574 | Fail-safe method and circuit A method and a circuit for producing a fail-safe output signal in case of an open circuit condition of an input pad of a digital circuit unit, comprising a first inverter stage providing a constant switch level; a second inverter stage providing a variable switch le... | 09/04/2007 |
| 7250786 | Method and apparatus for modular redundancy with alternative mode of operation A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of operation. Intelligent voting circuitry facilitates both modes of operation, while further enhancing the ro... | 07/31/2007 |
| 7236002 | Digital CMOS-input with N-channel extended drain transistor for high-voltage protection A circuit and a method are given, to realize an electronic system for combined usage at differing voltage ranges as defined by a low-voltage range for operating standard CMOS devices and a high-voltage range exceeding said standard CMOS low-voltage operating range s... | 06/26/2007 |
| 7236003 | H-bridge circuit with shoot through current prevention during power-up The H-bridge circuit with shoot through current prevention during power-up includes: a high side transistor; a low side transistor coupled in series with the high side transistor; pull down devices coupled to a control node of the high side transistor and to a contr... | 06/26/2007 |
| 7236340 | Gate control circuit for prevention of turn-off avalanche of power MOSFETs A switch in an inductive circuit is prevented from avalanche operation when the switch is turned off. By preventing avalanche, the associated EMI is reduced or eliminated. Switch avalanche can be prevented using an active component, such as a transistor, or a passiv... | 06/26/2007 |
| 7235999 | System monitor in a programmable logic device Method and apparatus for a system monitor embedded in a programmable logic device are described. The system monitor includes a dynamic reconfiguration port interface for configuring or reconfiguring the system monitor during operation thereof. The system monitor inc... | 06/26/2007 |
| 7236001 | Redundancy circuits hardened against single event upsets A decision block is incorporated into a circuit design to provide hardening against single event upset and to store data. The decision block includes a storage element that stores data as long as inputs to the decision block remain constant. The decision block recei... | 06/26/2007 |
| 7224178 | Circuit re-synthesis and method for delay variation tolerance By adding redundant logic gates into a circuit without changing function of the whole circuit, the present invention can tolerate certain delay variations. The present invention can be applied in the IC industries to improve the yield in semiconductor manufacturing.... | 05/29/2007 |
| 7215135 | Single event upset hardened circuitry without sensitivity to overshoot and/or undershoot conditions An apparatus for hardening logic circuitry against a Single-Event-Effect condition and for providing immunity to an overshoot and undershoot condition is provided. The apparatus includes undershoot-blocking and overshoot-blocking modules that are configured to be co... | 05/08/2007 |
| 7212027 | Disconnection and short detecting circuit that can detect disconnection and short of a signal line transmitting a differential clock signal Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted fro... | 05/01/2007 |
| 7200186 | Methods and apparatus for reducing power usage of a transmitter and receiver coupled via a differential serial data link Methods and apparatus are disclosed for using in-band signal(s) over a differential serial data link to reduce power usage of a transmitter and receiver coupled by the link. ... | 04/03/2007 |
| 7187991 | Failsafe control circuit for electrical appliances Failsafe control circuit for electrical appliances whereby at least one electrical load (10) is activated, the control circuit comprising logic control means (1), operation switching means (8) between said electrical load (10) and a suppl... | 03/06/2007 |
| 7176708 | Receiver circuit In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predet... | 02/13/2007 |
| 7170949 | Methods and apparatus for signaling on a differential link Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link. ... | 01/30/2007 |
| 7142004 | Radiation hardening of logic circuitry using a cross enabled, interlocked logic system and method A system and method for hardening a logic circuit against radiation-event effects is provided. The system may include a logic circuit, first and second feed-forward devices, and first and second feedback devices. The logic circuit may be operable to output independe... | 11/28/2006 |
| 7135885 | Dynamically adjustable signal detector A dynamically adjustable signal detector receives a differential input signal and outputs a signal indicative of whether a valid signal is being received based on dynamically adjustable threshold settings. The threshold settings can include differential voltage, pea... | 11/14/2006 |
| 7132857 | High speed receiver with wide input voltage range A receiver circuit (12) includes a first gate (24) that receives an input signal (VIN0, VIN1) and has an output (32, 34) for providing an output signal (VG0, VG1). A shifting circuit (20) is cou... | 11/07/2006 |
| 7123458 | Method and circuit arrangement for protecting an electric motor from an overload A method and a circuit for protecting an electric motor and/or its trigger circuit against overload in the emergency-operation mode in a motor vehicle direct-current fan motor operated by means of pulse width modulation, in which the trigger circuit is designed as a... | 10/17/2006 |
| 7103609 | System and method for analyzing usage patterns in information aggregates System and method for evaluating an information aggregate. A metrics database stores document indicia including document attributes, associated persons and usage metrics. A query engine collects a plurality of documents having non-unique values on a shared attribute... | 09/05/2006 |
| 7075328 | Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the rou... | 07/11/2006 |
| 7042251 | Multi-function differential logic gate A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be... | 05/09/2006 |