Class 326/13 - With field effect-transistor

Subclass of Class 326 - Electronic digital logic circuitry
Definition: Subject matter including a unipolar transistor in which
No. of patents: 62
Last issue date: 04/13/2010

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Number	Title	Issue Date
7696774	Systems and methods for providing defect-tolerant logic devices The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included w...	04/13/2010
7423448	Radiation hardened logic circuit A radiation-hardened logic circuit prevents SET-induced transient pulses from propagating through the circuit, using two identical logic paths. The outputs of the two logic paths are fed into an exclusive-OR gate, which controls gating circuitry. The gating circuitr...	09/09/2008
7411412	Semiconductor integrated circuit A semiconductor integrated circuit including: N modules set in their functions in accordance with input function setting data, a circuit block having R number of I/O parts, and a module selection part for selecting R number of modules from among the N number of modu...	08/12/2008
7317344	Function selection circuit using a fuse option scheme A semiconductor device is provided as a fuse option circuit. The semiconductor device is configured to include an input, a function selection fuse portion and a reset control circuit portion both connected to the input, and an output connected to the function select...	01/08/2008
7277346	Method and system for hard failure repairs in the field A semiconductor system and method for repairing failures of a packaged integrated circuit system are provided. The method includes detecting a failure associated with a packaged integrated circuit system after the packaged integrated circuit system is packaged, and ...	10/02/2007
7250796	Semiconductor device including an output circuit having a reduced output noise A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level...	07/31/2007
7236001	Redundancy circuits hardened against single event upsets A decision block is incorporated into a circuit design to provide hardening against single event upset and to store data. The decision block includes a storage element that stores data as long as inputs to the decision block remain constant. The decision block recei...	06/26/2007
7215135	Single event upset hardened circuitry without sensitivity to overshoot and/or undershoot conditions An apparatus for hardening logic circuitry against a Single-Event-Effect condition and for providing immunity to an overshoot and undershoot condition is provided. The apparatus includes undershoot-blocking and overshoot-blocking modules that are configured to be co...	05/08/2007
7180324	Redundancy structures and methods in a programmable logic device An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs fo...	02/20/2007
7043672	Layout for a semiconductor memory device having redundant elements The present invention reduces the area on a die required for rows and columns of redundant memory cells by sharing compare circuitry with banks of redundant memory cells based on division of the primary memory array into two or more “planes.” Pass gates or multi...	05/09/2006
7035152	System and method for redundancy memory decoding A redundancy system for disabling access to normal memory elements when memory addresses corresponding to those normal memory elements match programmed redundancy addresses before the memory addresses and the programmed redundancy addresses are compared. Access to t...	04/25/2006
7023235	Redundant single event upset supression system CMOS transistors are configured to operate as either a redundant, SEU-tolerant, positive-logic, cross-coupled Nor Gate SR-flip flop or a redundant, SEU-tolerant, negative-logic, cross-coupled Nand Gate SR-flip flop. The register can operate as a memory, and further ...	04/04/2006
6925024	Zero power chip standby mode A zero power standby mode in a memory device used in a system, such as a battery powered hand held device. By disconnecting the internal power supply bus on the memory device from the external power supply during standby mode, the junction leakage and gate induced d...	08/02/2005
6909659	Zero power chip standby mode A zero power standby mode in a memory device used in a system, such as a battery powered hand held device. By disconnecting the internal power supply bus on the memory device from the external power supply during standby mode, the junction leakage and gate induced d...	06/21/2005
6809545	Programmable power adjust for microelectronic devices A circuit to adjust power is disclosed. The circuit comprises at least one pass gate and a power adjustor electrically coupled to each pass gate such that the power adjustor consumes power when the gate is enabled. The power adjustor consumes power or not depending ...	10/26/2004
6801051	System and method for providing capacitive spare fill cells in an integrated circuit A processor includes an integer unit operable to execute integer instructions and a floating point unit operable to execute floating point instructions. The processor also includes at least one spare fill cell disposed in at least one portion of the processor that i...	10/05/2004
6794925	Cold spare circuit for CMOS output circuit A first cold spare circuit has first and second transistors, and a second cold spare circuit has third and fourth transistors. The first transistor has a gate controlled by a function of a first chip. A second transistor has its source and drain connected in series ...	09/21/2004
6756809	Single event upset immune logic family A collection of logic gates that provide single event upset (SEU) immunity. The family of gates include an inverter, a two-input NOR gate, a two-input NAND gate, a three-input AND-NOR gate, and a three-input OR-NAND as well as a static RAM bit cell. SEU immunity is ...	06/29/2004
6753694	Single event upset immune logic family A collection of logic gates that provide single event upset (SEU) immunity. The family of gates include an inverter, a two-input NOR gate, a two-input NAND gate, a three-input AND-NOR gate, and a three-input OR-NAND as well as a static RAM bit cell. SEU immunity is ...	06/22/2004
6703858	Logic architecture for single event upset immunity An SEU immune logic architecture includes a dual path logic gate coupled to a dual to single path converter. A first and a second logic element within the dual path logic gate are functionally and possibly structurally equivalent, and are coupled to recei...	03/09/2004
6614257	Logic architecture for single event upset immunity An SEU immune logic architecture includes a dual path logic gate coupled to a dual to single path converter. A first and a second logic element within the dual path logic gate are functionally and possibly structurally equivalent, and are coupled to recei...	09/02/2003
6486695	Protecting unit A protecting unit is provided. The protecting unit can prevent accidents from occurring that become problems when data are transmitted due to for instance LVDS and for instance laser light is emitted based on the data. The protecting unit is applied in an...	11/26/2002
6320405	Circuit for the switching of loads An apparatus for switching loads, based on a starting signal, having a first MOSFET output stage and a second downstream MOSFET output stage, each of the MOSFET output stages being controllable by a logic circuit, with a power supply voltage of the downst...	11/20/2001
6316956	Multiple redundant reliability enhancement method for integrated circuits and transistors In a fault-tolerant integrated power circuit, a plurality of power transistors, each having a power source electrically coupled to a common source line, a power gate and a power drain electrically coupled to a common drain line, is capable of driving a po...	11/13/2001
6278287	Isolated well transistor structure for mitigation of single event upsets CMOS circuits are made resistant to erroneous signals produced by the impact of high energy charged particles (commonly known in the literature as Single Event Upset or SEU) by the addition of upset immune transistor structures into the circuits in such a...	08/21/2001
6236241	Redundant decoder having fuse-controlled transistor A redundant decoder having fuse-controlled transistor comprises as follows: a bistable circuit which outputs a pair of complementary signals; a discharging device which is turned on at an evaluating cycle to form a discharging path; a precharging device w...	05/22/2001
6175938	Scheme for the reduction of extra standby current induced by process defects A scheme for reduction of extra standby current induced by process defects is disclosed. After the bit lines and cells with failure due to process defects are repaired by using redundancy in the repairing process, the fuses connected with the pull-transis...	01/16/2001
6125069	Semiconductor memory device with redundancy circuit having a reference resistance A semiconductor memory device with a redundancy circuit includes a reference section, a fuse section and a latch section. The reference section includes a reference resistance and supplies a first current to the reference resistance. The fuse section incl...	09/26/2000
6104211	System for preventing radiation failures in programmable logic devices A radiation-tolerant logic circuit includes three similarly configured SRAM-based PLDs. These PLDs work in parallel to provide identical logic functions. To guard against data corruption that can result from radiation-induced upsets, the logic circuit inc...	08/15/2000
5925920	Techniques and circuits for high yield improvements in programmable devices using redundant routing resources The present invention provides a method and apparatus for high yield improvements in programmable logic devices using redundancy. The present invention concerns a programmable logic device comprising a plurality of routings lines coupled to a plurality of...	07/20/1999
5731716	Programmable multibit register for coincidence and jump operations and coincidence fuse cell A programmable cell and a multibit register composed of a plurality of such cells, specifically for performing a coincidence check between a certain code permanently recorded in the cell or cells and a logic configuration present on a pair or on a plurali...	03/24/1998
5576633	Block specific spare circuit A circuit for selecting a block spare in a semiconductor device is designed with a programmable circuit (14), storing an internal address and producing an address match signal AM and a block select signal BS in response to first (A) and second (B) address...	11/19/1996
5568061	Redundant line decoder master enable A master enable circuit is provided which receives multiple enable signal inputs while matching the redundant decoder enable delay with decoder enable delay. A master enable circuit contains a hard coded master fuse, driver transistor, and a multiple inpu...	10/22/1996
5548225	Block specific spare circuit A circuit for selecting a block spare in a semiconductor device is designed with a programmable circuit (14), storing an internal address and producing an address match signal AM and a block select signal BS in response to first (A) and second (B) address...	08/20/1996
5543736	Gate array architecture and layout for deep space applications The present invention teaches an integrated circuit ("IC") gate array having improved reliability and increased immunity to deep space interference from electromagnetic radiation, photon energy, and charged particles. In one embodiment of the present inve...	08/06/1996
5422850	Semiconductor memory device and defective memory cell repair circuit To provide a type of semiconductor memory device characterized by the fact that the redundancy for the defective memory of defective bits is increased and the area occupied by the redundant memory address decoder on the chip is minimized, thereby reducing...	06/06/1995
5396124	Circuit redundancy having a variable impedance circuit In a semiconductor memory having a redundant circuit, a plurality of first normal cells and a plurality of first spare cells are connected to a first pair of data lines, and a plurality of second normal cells and a plurality of second spare cells are conn...	03/07/1995
5387823	Fuse-programmable redundancy control circuit A fuse-programmable control circuit has a master control circuit with a first fusible link that controls the feeding of power to a fuse-programmable memory. If output of signals from the fuse-programmable memory is not required, the first fusible link is ...	02/07/1995
5369314	Programmable logic device with redundant circuitry A programmable logic device is provided that has redundant circuitry. When a portion of the programmable logic device circuitry is found to be defective, the redundant circuitry is switched into use in place of the defective circuitry by programming appro...	11/29/1994
5345110	Low-power fuse detect and latch circuit This invention is a low-power circuit for detecting and latching the state of a fusible link. During a power-up sequence, the circuit makes a one time determination regarding the blown or unblown status of a fuse element. In one embodiment of the inventio...	09/06/1994

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Class 326/13 - With field effect-transistor