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| Number | Title | Issue Date |
| 7474126 | Parallel bipolar logic devices and methods for using such Various logic gates and methods for using such are disclosed herein. For example, some embodiments of the present invention provide parallel differential logic gates. Such logic gates include two or more differential input pairs. The collectors of the first transist... | 01/06/2009 |
| 7408384 | Drive circuit of computer system for driving a mode indicator A drive circuit of a computer system is for driving a mode indicator. The computer system includes a first port and a second port. The mode indicator includes a first receiving end and a second receiving end. The drive circuit includes a first input end connected to... | 08/05/2008 |
| 7348818 | Tunable high-speed frequency divider A locking range of a current mode logic (CML) frequency divider circuit is tunable by dynamically adjusting a tail current of the frequency divider circuit according to a control signal. The control signal may be based on at least one control signal coupled to tune ... | 03/25/2008 |
| 7339402 | Differential amplifier with over-voltage protection and method Circuitry for preventing damage to bipolar transistors in integrated circuit amplifier circuitry during slew-limited operation includes first and second transistors, each having first, second, and third electrodes, a first one of the first and second electrodes of t... | 03/04/2008 |
| 7331830 | High-density orthogonal connector A high-density orthogonal connector is disclosed and may include electrical contacts that are configured to receive contacts from an orthogonal header connector while minimizing signal skew and signal reflection. The electrical contacts in the connector may define c... | 02/19/2008 |
| 7327165 | Drive circuit of computer system for driving a mode indicator A drive circuit of a computer system is for driving a mode indicator. The computer system includes a first port and a second port. The mode indicator includes a first receiving end and a second receiving end. The drive circuit includes a first input end connected to... | 02/05/2008 |
| 7312639 | Universal single-ended parallel bus A high speed data communication system uses a single-ended bus architecture with a reference signal extracted from a differential periodic signal that is transmitted along with single-ended data. By using a periodic signal such a clock signal with approximately 50% ... | 12/25/2007 |
| 7301371 | Transmitter of a semiconductor device Embodiments of the present invention provide a transmitter of a semiconductor device, which can output signals corresponding to input signals having various common mode levels and amplitudes. The transmitter may include a pre-driver unit, main driver unit, and a con... | 11/27/2007 |
| 7288971 | Systems and methods for actively-peaked current-mode logic A method and apparatus for creating high speed logic circuits in a CMOS environment using current steering logic cells with actively-peaked NMOS or PMOS loads and the biasing of these logic cells is disclosed. The logic cells can include, for example, buffers, AND g... | 10/30/2007 |
| 7288857 | Self-latching power supply apparatus A self-latching power supply apparatus is disclosed. The apparatus comprises an activation transistor in electrical communication with an input voltage source and a battery-switching transistor. Voltage detection circuitry may be intermediate the input voltage sourc... | 10/30/2007 |
| 7263628 | Method and apparatus for receiver circuit tuning A Mobile Subscriber Directory Assistance (MSDA) system including originating carrier center initiating a directory assistance call, a directory assistance center providing a directory assistance service, and a search environment. The search environment includes an a... | 08/28/2007 |
| 7250790 | Circuit for providing a logic gate function and a latch function An electronic circuit for providing a logic gate function includes a differential signal input, a combining stage, a discriminating stage and a differential signal output. The discriminating stage includes four transistors each having first electrodes and second ele... | 07/31/2007 |
| 7242113 | Power semiconductor device A power semiconductor device which makes a heat come hard to arise in a particular element and is able to control an increase of the amount of a power loss caused by a tail current, even in case that plural power semiconductor elements are connected in parallel is p... | 07/10/2007 |
| 7230459 | Static frequency divider for microwave applications A static frequency divider circuit includes a first and second latch that are interconnected by a series path circuit and by a feedback path circuit. Each of the latches includes a reading BALLSACKbranch and a latching branch. The series path circuit includes a push... | 06/12/2007 |
| 7218145 | Level conversion circuit An input circuit (a first transistor pair) that receives complementary input signals is connected to a latch circuit (a second transistor pair) that converts the amplitude of an input signal into second amplitude higher than first amplitude. A current mirror circuit... | 05/15/2007 |
| 7215170 | Low voltage logic circuit with set and/or reset functionality A low voltage logic circuit with asynchronous SET and/or RESET functions is described herein. The low voltage logic circuit may be primarily used in forming low voltage flip-flop circuits, but may also be used to form multiplexers and other logic configurations. The... | 05/08/2007 |
| 7205796 | AND circuit An AND circuit is provided, which has a first differential pair including a first transistor and a second transistor, to which a first input differential signal is inputted, a second differential pair including a third transistor and a fourth transistor, to which a ... | 04/17/2007 |
| 7202696 | Circuit for temperature and beta compensation A compensation circuit is disclosed. The compensation circuit includes a driver stage having an output, a differential output device including a base coupled to the output of the driver stage, and a feedback block coupled to a first emitter of the differential outpu... | 04/10/2007 |
| 7203859 | Variable clock configuration for switched op-amp circuits A clock configuration for driving switched op-amp circuits operated in opposite phases is presented in which a common off-phase of variable length is inserted between the on-phases of the individual operational amplifiers. The length of the off-phase can be adapted ... | 04/10/2007 |
| 7202706 | Systems and methods for actively-peaked current-mode logic A method and apparatus for creating high speed logic circuits in a CMOS environment using current steering logic cells with actively-peaked NMOS or PMOS loads and the biasing of these logic cells is disclosed. The logic cells can include, for example, buffers, AND g... | 04/10/2007 |
| 7199619 | High-speed differential logic multiplexer A circuit for a high speed digital multiplexer has an active load circuit connected to an output of the digital multiplexer. The active load circuit loads the multiplexer output with a transimpedance stage with low input resistance to reduce the RC time constant at ... | 04/03/2007 |
| 7187207 | Leakage balancing transistor for jitter reduction in CML to CMOS converters The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled ... | 03/06/2007 |
| 7187212 | System and method for providing a fast turn on bias circuit for current mode logic transmitters A system and method is disclosed for providing a fast turn on bias circuit that permits a fast transition from an idle “power down” state to an active “power up” state in current mode logic (CML) transmitter output circuits. The invention comprises a capacit... | 03/06/2007 |
| 7187208 | Complimentary metal oxide silicon low voltage positive emitter coupled logic buffer A low voltage positive emitter coupled logic (LV-PECL) buffer fabricated in the complimentary oxide metal silicon (CMOS) process. The LV-PECL buffer in CMOS is operable for a wide frequency range from DC to frequencies as high as 800 MHZ in 0.5 um process. Synchroni... | 03/06/2007 |
| 7183832 | Level shifter with boost and attenuation programming A level shifter circuit includes a bias module that receives a first voltage value, that generates a second voltage value when an operational frequency of the level shifter circuit is less than a threshold, and that generates a third voltage value when the operation... | 02/27/2007 |
| 7180352 | Clock recovery using clock phase interpolator A clock recovery circuit includes a delay locked loop, and a clock phase interpolator circuit. The delay locked loop provides multiple phases of an input clock signal to the interpolator circuit, which interpolates between two of the clock phases to provide a clock ... | 02/20/2007 |
| 7180310 | Amplitude varying driver circuit and test apparatus There is provided an amplitude varying driver circuit operable to output an output signal, which is an amplified input signal being supplied. The amplitude varying driver circuit includes: a plurality of differential amplifiers provided in parallel with one another,... | 02/20/2007 |
| 7157809 | Method and circuits for inductive DC converters with current regulated output A method and circuits for improving the inductive DC converter delivery of regulated current into the load(s), where the inductive DC converter provides the output voltage to an ensemble consisting of the load(s) and a current source or a current source circuit conn... | 01/02/2007 |
| 7154301 | Apparatus and method for a low jitter predriver for differential output drivers A method and apparatus for a low jitter predriver for differential output drivers. In one embodiment, the predriver comprises a pull-up circuit having at least one pull-up device of a first device type and a pull-down circuit having at least one pull-down device of ... | 12/26/2006 |
| 7148724 | Signal output circuit The signal output circuit 1 includes a first and a second emitter follower circuit, and a comparator 20. The comparator 20 receives output signals from the first and the second emitter follower circuit, and outputs a result of comparison in magn... | 12/12/2006 |
| 7145366 | Electronic circuit with a differential pair of transistors and logic gate comprising such a circuit An electronic circuit includes at least one differential pair of transistors, a control transistor switch, a first current source and a second current source. The second current source is connected to a common emitter node of the pair of transistors in order to acce... | 12/05/2006 |
| 7135929 | Bias voltage circuit with ultra low output impedance A bias voltage circuit with ultra low output impedance. The circuit incorporates feedback to reduce the output impedance at both low and RF frequencies. The bias circuit outputs a bias signal for biasing an amplifier. The bias circuit includes an input stage that re... | 11/14/2006 |
| 7132848 | Power management circuit A power management circuit. A logic cell switched between normal and standby modes according to a power control signal includes a plurality of first NMOS transistors coupled between at least one complementary pair of data signal inputs and a complementary pair of da... | 11/07/2006 |
| 7129742 | Majority logic circuit A novel majority logic circuit is disclosed to determine whether the majority of the inputs are a one, within a constant number of clock cycles, regardless of the number of inputs. The majority logic circuit according to the present invention includes a plurality of... | 10/31/2006 |
| 7119549 | Output calibrator with dynamic precision An integrated circuit device having an output driver circuit and a control circuit. The output driver circuit outputs a first signal having a signal level according to a control value. The control circuit is coupled to receive the first signal from the output driver... | 10/10/2006 |
| 7106093 | Semiconductor device A semiconductor device having a plurality of cascaded IC's (14, 15, 16), wherein the matching impedance between a signal transmission path (12) connected to an external signal transmission path and an input-side or output-side IC (14, 16) is set... | 09/12/2006 |
| 7106104 | Integrated line driver The present invention provides integrated line drivers useable for driving data signals with high data rates wherein the area consumption of the line driver is minimized and wherein the influence of electrostatic discharge devices and process tolerances are minimize... | 09/12/2006 |
| 7098697 | Low voltage high-speed differential logic devices and method of use thereof A circuit topology for high speed low voltage logic circuits is disclosed that reduces the number of levels of stacked active circuit elements from 3 to 2. Circuits providing a variety of logic functions are presented, including a latch, an exclusive OR gate, a comb... | 08/29/2006 |
| 7049858 | Reducing transient current caused by capacitance during high speed switching An isolation resistor is inserted in series between a current source and the emitters of bipolar switching transistors in a differential amplifier. The switching transistors may also be MOSFETs. The in-rush current through the resistor, due to a parasitic or added c... | 05/23/2006 |
| 7046072 | Commutating phase selector A phase selector for selecting a differential output can include two matched transistor circuits. A first transistor circuit can receive a first differential input signal whereas a second transistor circuit can receive a second differential input signal. One of the ... | 05/16/2006 |
