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| Number | Title | Issue Date |
| 8188767 | Logic circuit and method of logic circuit design A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for ... | 05/29/2012 |
| 8120384 | Multivalued logic circuit In a bridge adder circuit, a first and a second complementary pair of current mirrors is connected between the input terminals and a positive and a negative supply voltage bus, respectively, to control a first and a second push-pull output stage. The outputs of the ... | 02/21/2012 |
| 8111089 | Building block for a secure CMOS logic cell library A logical building block and method of using the building block to design a logic cell library for CMOS (Complementary Metal Oxide Silicon) ASICs (Application Specific Integrated Circuits) is disclosed. Different logic gates, built with the same building block as de... | 02/07/2012 |
| 8030971 | High-density logic techniques with reduced-stack multi-gate field effect transistors Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required ... | 10/04/2011 |
| 8004316 | Logic circuit and method of logic circuit design A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for ... | 08/23/2011 |
| 7986167 | Circuit configurations having four terminal devices Circuits using four terminal transistors are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four te... | 07/26/2011 |
| 7919990 | Semiconductor device A semiconductor device of the present invention comprises an SGT based, at least two-stage CMOS inverter cascade circuit configured to allow a pMOS SGT to have a gate width two times greater than that of an nMOS SGT. A first CMOS inverter includes two pMOS SGT arran... | 04/05/2011 |
| 7876131 | Dual gate transistor keeper dynamic logic A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its inp... | 01/25/2011 |
| 7859312 | Multivalued logic circuit In a bridge adder circuit, a first and a second complementary pair of current mirrors is connected between the input terminals and a positive and a negative supply voltage bus, respectively, to control a first and a second push-pull output stage. The outputs of the ... | 12/28/2010 |
| 7804332 | Circuit configurations having four terminal JFET devices Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or an... | 09/28/2010 |
| 7804331 | Semiconductor device A semiconductor device according to an embodiment of the present invention includes an output stage circuit including a first conductive type first transistor and a second conductive type second transistor, the first conductive type first transistor being connected ... | 09/28/2010 |
| 7710160 | Stacked inverter delay chain Stacked inverter delay chains. In accordance with a first embodiment of the present invention, a series stack of two p-type devices is coupled to a series stack of three n-type devices, forming a stacked inverter comprising desirable delay, die area and power charac... | 05/04/2010 |
| 7659751 | Multiple-output transistor logic circuit A method of designing logic circuit provides a logic circuit which includes a first transistor network and a complementary second transistor network connected at a central node. The central node serves as a first logic output. Each of the transistor networks is also... | 02/09/2010 |
| 7642813 | Error correcting logic system The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redu... | 01/05/2010 |
| 7629815 | Low-power semi-dynamic flip-flop with smart keeper A modified high-speed flip-flop including an input circuit, a smart window circuit, a smart keeper circuit, a pre-charge circuit, a discharge circuit, a slave storage circuit, and an output circuit. Additionally, a circuit including the modified high-speed flip-flop... | 12/08/2009 |
| 7602219 | Inverting cell An inverting cell including a first inverter having first and second inputs; a second inverter having first and second inputs, wherein the second input of the second inverter is connected to the first input of the first inverter and the output of the first and secon... | 10/13/2009 |
| 7598774 | Reduced power consumption limited-switch dynamic logic (LSDL) circuit An limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock signal having a reduced voltage swing in the evaluation phase, the LSDL gates are permitted to operate, while r... | 10/06/2009 |
| 7592842 | Configurable delay chain with stacked inverter delay elements A stacked inverter delay chain. The stacked inverter delay chain includes a plurality of stacked inverter delay elements. A switch circuit is included and is coupled to the stacked inverter delay elements and configured to select at least one of the plurality of sta... | 09/22/2009 |
| 7592841 | Circuit configurations having four terminal JFET devices Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or an... | 09/22/2009 |
| 7576568 | Self-selecting precharged domino logic circuit A domino logic circuit having an input terminal and a precharge node. A first switch is responsive to a second switch sensing one of a high or low voltage at the precharge node to charge the precharge node and the second switch is responsive to the one of a high or ... | 08/18/2009 |
| 7570081 | Multiple-output static logic An approach is provided in embodiments of the present invention for building multiple-output static CMOS logic gate circuits that share transistors when computing multiple functions from a common set of inputs. In particular, an approach is provided which includes b... | 08/04/2009 |
| 7557618 | Conditioning logic technology Conditioning logic modifies the electrical characteristics of conventional logic circuits to improve speed, power, and timing margins. This is accomplished by adding circuitry to pre-condition the state of the circuit to optimize any desired transition. Basic functi... | 07/07/2009 |
| 7436212 | Interface circuit power reduction Embodiments of the invention provide an interface circuit that is capable of reducing the power consumption, which may be increased by a shoot-through current, and provide an electronic device having such an interface circuit. In one embodiment, an interface circuit... | 10/14/2008 |
| 7417465 | N-domino output latch An N-domino latch includes a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage is coupled to an approximately symmetric clock signal. The domino stage evaluates a logic function according to the st... | 08/26/2008 |
| 7414436 | Limited switch dynamic logic cell based register A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the fron... | 08/19/2008 |
| 7411425 | Method for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit A method for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock signal having a reduced voltage swing in the evaluation phase, the L... | 08/12/2008 |
| 7388406 | CML circuit devices having improved headroom A CML digital circuit includes a load coupled between a power supply node and at least one output node and a logic circuit component coupled to the output node. The logic circuit component has at least one data input node. The logic circuit component comprises a fir... | 06/17/2008 |
| 7389478 | System and method for designing a low leakage monotonic CMOS logic circuit A low leakage monotonic CMOS logic circuit and a method, a method of design and a system for designing such circuits. The circuit, including: one or more logic stages, at least one of the logic stages having a predominantly high input state or having a predominantly... | 06/17/2008 |
| 7385426 | Low current offset integrator with signal independent low input capacitance buffer circuit A buffer circuit (318) including a first half circuit and a second half circuit. Each half circuit includes a first MOS transistor (M4, M9) as the input device and a source follower, a second MOS transistor (M23, M22) as a transcon... | 06/10/2008 |
| 7382161 | Accelerated P-channel dynamic register A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal, and opens an evaluation window when the pulsed clock signal goes low,... | 06/03/2008 |
| 7382162 | High-density logic techniques with reduced-stack multi-gate field effect transistors Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required ... | 06/03/2008 |
| 7372305 | Scannable dynamic logic latch circuit A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a scan pull-down logic tree that is coupled to a scan hold latch outpu... | 05/13/2008 |
| 7365576 | Binary digital latches not using only NAND or NOR circuits A switching model to create stable binary sequential devices comprised of one or more logic functions with feedback of which an output signal is uniquely related to an input signal is applied to possible binary logic functions. Static latches of commutative and non-... | 04/29/2008 |
| 7365582 | Bootstrapped charge pump driver in a phase-lock loop A charge pump includes first and second pairs of differential transistors. Each transistor includes control, first, and second terminals. First and second charge pump drivers communicate with the control terminal of one of the first pair of differential transistors ... | 04/29/2008 |
| 7365587 | Contention-free keeper circuit and a method for contention elimination A contention-free keeper circuit including a keeper circuit having a first node and a second node, is provided. The contention-free keeper circuit may further include a delay element for providing time delay. The contention-free keeper circuit may further include a ... | 04/29/2008 |
| 7362140 | Low swing current mode logic family The present invention provides a low swing current mode logic circuit including: a current mode logic block having data inputs and outputs; a pre-charging circuit for pre-charging the outputs; a dynamic current source; an evaluation circuit for evaluating the logic ... | 04/22/2008 |
| 7362134 | Circuit and method for latch bypass A device includes a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypa... | 04/22/2008 |
| 7358718 | Semiconductor device and electronics device A plurality of switch circuits are disposed so as to correspond to a plurality of circuit blocks, respectively. Each of the plurality of switch circuits is connected between a power supply terminal of a corresponding circuit block and a power supply line. A setting ... | 04/15/2008 |
| 7355455 | Low power consumption MIS semiconductor device A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the su... | 04/08/2008 |
| 7355447 | Level shifter circuit A level shifter is disclosed. The level shifter includes a level shifter core circuit and a pull-up control logic circuit. In response to an input signal and an output signal of the level shifter core circuit, the pull-up control logic circuit selectively turns on a... | 04/08/2008 |
