Class 326/12 - With flip-flop

Subclass of Class 326 - Electronic digital logic circuitry
Definition: Subject matter comprising a logic circuit which has two
No. of patents: 31
Last issue date: 12/20/2011

Number	Title	Issue Date
8081010	Self restoring logic Self Restoring Logic (SRL) provides for SEU tolerance in high speed circuits. An SRL cell is designed to be stable in one of two internal states. Upon an SEU event, the SRL cell will not transition between the internal stable states and recover from an SEU. SRL circ...	12/20/2011
8054099	Method and apparatus for reducing radiation and cross-talk induced data errors The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a num...	11/08/2011
7948261	Semiconductor integrated circuit device and countermeasure method against NBTI degradation A semiconductor integrated circuit device includes a target circuit of a low power consumption mode having at least one flip-flop circuit to which a clock signal is supplied in a normal operation mode and in a low power consumption mode, and a logic circuit to which...	05/24/2011
7902856	Semiconductor integrated circuit An exemplary aspect of the invention is to conduct delay tests under actual operating conditions for a semiconductor integrated circuit including multiple logic circuits operating based on clocks of different frequencies, without causing any inconveniences when a te...	03/08/2011
7482831	Soft error tolerant flip flops A register designed to detect and correct soft errors in real time. A redundant latch is added to the existing structure of a flip flop and functional data is simultaneously registered at multiple latches. The content of these multiple latches are fed to a majority ...	01/27/2009
7411412	Semiconductor integrated circuit A semiconductor integrated circuit including: N modules set in their functions in accordance with input function setting data, a circuit block having R number of I/O parts, and a module selection part for selecting R number of modules from among the N number of modu...	08/12/2008
7411411	Methods and systems for hardening a clocked latch against single event effects Methods and systems for hardening a clocked latch against single event effects are disclosed. A system includes a first three-input OR gate, a first NAND gate, a second three-input OR gate, and a second NAND gate. The first three-input OR gate receives as inputs a c...	08/12/2008
7277346	Method and system for hard failure repairs in the field A semiconductor system and method for repairing failures of a packaged integrated circuit system are provided. The method includes detecting a failure associated with a packaged integrated circuit system after the packaged integrated circuit system is packaged, and ...	10/02/2007
7236001	Redundancy circuits hardened against single event upsets A decision block is incorporated into a circuit design to provide hardening against single event upset and to store data. The decision block includes a storage element that stores data as long as inputs to the decision block remain constant. The decision block recei...	06/26/2007
7215140	Programmable logic device having regions of non-repairable circuitry within an array of repairable circuitry and associated configuration hardware and method An embodiment of the present invention provides a programmable logic device (“PLD”) including one or more dedicated blocks of circuitry within one or more repairable logic array regions. Aspects of the present invention provide circuitry and methods for controll...	05/08/2007
7126369	Transceiver providing high speed transmission signal using shared resources and reduced area A transceiver provides a high-speed transmission signal using shared resources and reduced area. A differential amplifier has its current source/sink connected to a supply terminal. A multiplexing circuit is configured to connect an input of the differential amplifi...	10/24/2006
7071725	Data processing apparatus and logical operation apparatus A data processing apparatus comprises a plurality of input signal lines, a plurality of output signal lines and an electronic circuit. The electronic circuit inputs first data from the plurality of input signal lines and outputs second data to the plurality of outpu...	07/04/2006
7023235	Redundant single event upset supression system CMOS transistors are configured to operate as either a redundant, SEU-tolerant, positive-logic, cross-coupled Nor Gate SR-flip flop or a redundant, SEU-tolerant, negative-logic, cross-coupled Nand Gate SR-flip flop. The register can operate as a memory, and further ...	04/04/2006
6756808	Clock edge detection circuit The clock edge detection circuit is equipped with a first delay circuit 11 that delays a first clock signal and outputs a first delay clock signal, a second delay circuit 21 that delays a second clock signal and outputs a second delay clock signal, a f...	06/29/2004
6570402	Impedance control circuit An impedance control circuit designed to match the impedance between a semiconductor device and a transmission medium (PCB) by using a current source installed in the semiconductor device instead of using an external resistor is provided. Since the impeda...	05/27/2003
6480019	Multiple voted logic cell testable by a scan chain and system and method of testing the same A multiple voted integrated circuit logic cell testable by a scan chain comprises: an odd plurality of latching registers, each register having a data input for receiving a scan chain data signal and capable of latching the scan chain data signal and gene...	11/12/2002
6417710	Single event upset hardened latch circuit A single event upset (SEU) hardened latch circuit utilizing two cross-coupled inverters in which the voter output circuitry is fed back to the output node of the latch circuit....	07/09/2002
6377071	Composite flag generation for DDR FIFOs An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate (i) one or more first enable signals and (ii) one or more first flag signals in response to a first clock signal and a second en...	04/23/2002
6320405	Circuit for the switching of loads An apparatus for switching loads, based on a starting signal, having a first MOSFET output stage and a second downstream MOSFET output stage, each of the MOSFET output stages being controllable by a logic circuit, with a power supply voltage of the downst...	11/20/2001
6125069	Semiconductor memory device with redundancy circuit having a reference resistance A semiconductor memory device with a redundancy circuit includes a reference section, a fuse section and a latch section. The reference section includes a reference resistance and supplies a first current to the reference resistance. The fuse section incl...	09/26/2000
6104211	System for preventing radiation failures in programmable logic devices A radiation-tolerant logic circuit includes three similarly configured SRAM-based PLDs. These PLDs work in parallel to provide identical logic functions. To guard against data corruption that can result from radiation-induced upsets, the logic circuit inc...	08/15/2000
6094385	Repairable memory cell for a memory cell array An array of memory cells including a first block of memory cells having a first replacement column of memory cells is provided. The first replacement column is able to replace any defective column of memory cells in the first block. To accomplish this, a ...	07/25/2000
5508634	Semiconductor integrated circuit device of dual configuration having enhanced soft error withstanding capacity A semiconductor integrated circuit device has a dual configuration involving a first latch circuit and a second latch circuit that are connected in parallel with each other. The first latch circuit is provided with an input terminal to operate the first l...	04/16/1996
5436572	Semiconductor integrated circuuit device of dual configuration having enhanced soft error withstanding capacity A semiconductor integrated circuit device has a dual configuration involving a first latch circuit and a second latch circuit that are connected in parallel with each other. The first latch circuit is provided with an input terminal to operate the first l...	07/25/1995
5434514	Programmable logic devices with spare circuits for replacement of defects A programmable, integrated circuit, logic array device has several regular logic groups and at least one spare logic group. If any of the regular logic groups is defective, the spare logic group is used to make up for the defective logic group. To accompl...	07/18/1995
5087839	Method of providing flexibility and alterability in VLSI gate array chips A method and technique for inserting additive logic and flip-flops into the architecture of a gate array chip package whereby spare input and output pins can later be used to alter the logic functions by either disabling or enabling certain logic units in...	02/11/1992
4849657	Fault tolerant integrated circuit design A fault-tolerant digital integrated circuit includes functionally identical circuit blocks, each of such identical circuit blocks having an input region and an output region. The input regions receive identical input signals and the output regions are ele...	07/18/1989
4641285	Line change-over circuit and semiconductor memory using the same The line change-over circuit suitable for the semiconductor memory having a redundancy memory column comprises a pair of transfer gate elements provided between a first node to which a first signal to be transmitted is supplied and a pair of transmission ...	02/03/1987
4614881	Integrated semiconductor circuit device for generating a switching control signal using a flip-flop circuit including CMOS FET's and flip-flop setting means An integrated semiconductor circuit device for generating a switching control signal includes a fuse having one terminal connected to a power source, and the other terminal connected to a flip-flop circuit comprising a cross-connected pair of complementar...	09/30/1986
4475049	Redundant serial communication circuit A circuit for carrying data between a host system and a remote unit includes first and second edge-triggered delay-type flip-flops coupled to first and second input lines, respectively. Combinational logic coupled to the output of the first flip-flop and ...	10/02/1984
4213064	Redundant operation of counter modules Redundant operation of counter modules is maintained by detecting the zero state of each counter and clearing the other to that state, thus periodically resynchronizing the counters, and obtaining an output from both counters through AC coupled diode-OR g...	07/15/1980

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Class 326/12 - With flip-flop