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Actor Marlon Brando has four patents, all named "Drumhead tensioning device and method."
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| Number | Title | Issue Date |
| 8143919 | Semiconductor device and a display device The invention provides a low cost and high performance functional circuit by reducing time required for the repetition of logic synthesis and routing of layout in a functional circuit design. A standard cell used for the logic synthesis and the routing of layout is ... | 03/27/2012 |
| 7456660 | Semiconductor device and display device The invention provides a low cost and high performance functional circuit by reducing time required for the repetition of logic synthesis and routing of layout in a functional circuit design. A standard cell used for the logic synthesis and the routing of layout is ... | 11/25/2008 |
| 7394294 | Complementary pass-transistor logic circuit and semiconductor device A complementary pass-transistor logic includes input nodes provided with first complementary signals; intermediate nodes for outputting complementary intermediate signals; a logic network comprised of NMOS transistors, the network being connected between the input n... | 07/01/2008 |
| 7342423 | Circuit and method for calculating a logical combination of two input operands A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle, a second input for receiving a... | 03/11/2008 |
| 7342307 | Semiconductor device A semiconductor device includes: a package; two semiconductor chip fixing parts located adjacently to each other in the package; and first and the second semiconductor chips, each of which is fixed on the semiconductor chip fixing part and has a field effect transis... | 03/11/2008 |
| 7279936 | Logic basic cell, logic basic cell arrangement and logic device A logic basic cell, a logic basic cell arrangement, and a logic device. A logic basic cell is provided for forming a logic combination of two data signals in accordance with a logic function that can be selected by means of a plurality of logic selection elements, h... | 10/09/2007 |
| 7265580 | Semiconductor-integrated circuit utilizing magnetoresistive effect elements A semiconductor integrated circuit device has a plurality of circuit elements, a plurality of connection elements each of which becomes a conductive state or a nonconductive state, interconnects for supplying control signals for placing the connection elements in th... | 09/04/2007 |
| 7256622 | AND, OR, NAND, and NOR logical gates A logic family consisting of four basic logical circuits performing AND, OR, NAND and NOR functions is disclosed. The AND and OR logic circuits function without a power supply and complementary input signals. The NAND and NOR logic circuits function without compleme... | 08/14/2007 |
| 7203789 | Architecture and methods for computing with reconfigurable resistor crossbars An architecture for computing includes nanometer scale crossbar switches configured to perform a logical function in response to a sequence of pulses that encode logic values in the nanometer scale crossbar switches as impedances. ... | 04/10/2007 |
| 7187207 | Leakage balancing transistor for jitter reduction in CML to CMOS converters The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled ... | 03/06/2007 |
| 7176715 | Computer combinatorial multipliers in programmable logic devices Disclosed is a device and method for configuring a register in a PLD to operate as a logical AND gate. So configuring a register allows it to be used in a multiplication carried out by the PLD. A logic element includes a combinatorial logic section and at least one ... | 02/13/2007 |
| 7161389 | Ratioed logic circuits with contention interrupt A ratioed logic gate includes a contention interrupt circuit. The ratioed logic gate includes a pull up network coupled to a pull down network. Multiple inputs are coupled to turn the pull down and pull up networks on and off. An output is coupled to apply a logical... | 01/09/2007 |
| 7102202 | Display unit, drive circuit, amorphous silicon thin-film transistor, and method of driving OLED A display unit has an organic light emitting diode (OLED) 21 provided in correspondence with each of pixels and capable of emitting light by itself, a drive transistor 22 for driving the OLED 21, a twig transistor 23 which is formed so as... | 09/05/2006 |
| 7068063 | Output buffer circuit An output buffer circuit includes first and second inverters connected to an input terminal for outputting signals having a slow rise up and fall down characteristic; a pull up control circuit that pulls up an output voltage of the first inverter and stops the pull ... | 06/27/2006 |
| 6998877 | High speed differential signaling logic gate and applications thereof A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, current source, a 1st load, and a 2nd load. The 1st input transistor is operably co... | 02/14/2006 |
| 6972598 | Methods and arrangements for an enhanced scanable latch circuit Methods, and arrangements to enhance speed and reduce power consumption in a scanable latch circuit are disclosed. Embodiments include a wired-or circuit to facilitate independent paths for scan data and normal input data through the scanable latch circuit. In parti... | 12/06/2005 |
| 6954451 | Distributed time-multiplexed bus architecture and emulation apparatus A time-multiplexed data bus driver circuit includes a plurality of combinatorial circuits, each of the circuits forming a logic combination of a datum value, a datum enable signal and a datum timeslot signal, the plurality of circuits producing a plurality of output... | 10/11/2005 |
| 6891398 | Skewed falling logic device for rapidly propagating a falling edge of an output signal The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates... | 05/10/2005 |
| 6820242 | Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit To produce a logic circuit with excellent characteristics including area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function. Respective nodes are mapped ... | 11/16/2004 |
| 6794902 | Virtual ground circuit Methods and systems for improving a logic circuit are described. By using a voltage reducer for connecting a power-supply to a virtual ground, the voltage reducer reduces the voltage supplied by the power-supply to the virtual ground during one phase of the clock, t... | 09/21/2004 |
| 6720797 | Pass transistor circuit with exclusive controls A pass transistor circuit comprises a plurality of pass transistors connected in parallel. The same input signal is inputted into the sources of these pass transistors. Continuities of these pass transistors are controlled by a plurality of control signals having an... | 04/13/2004 |
| 6674308 | Low power wired OR A low power wired OR circuit of the present invention comprises a plurality of logic blocks for pulling a wired OR signal line low in response to certain conditions, a differential pair of lines, such as the wired OR signal line and a reference signal lin... | 01/06/2004 |
| 6448818 | Apparatus, method and system for a ratioed NOR logic arrangement A ratioed NOR gate arrangement for low-voltage-swing logic circuit arrangements, the ratioed NOR gate arrangement including at least two input terminals, an output terminal, and two inverter arrangements, in which each of the two inverter arrangements is ... | 09/10/2002 |
| 6433588 | Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit In order to produce a logic circuit excellent in circuit characteristics which are area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function, an... | 08/13/2002 |
| 6420906 | FET-OR circuit and power supply circuit using the same An OR circuit allowing one stable output voltage from a plurality of input voltages is disclosed. A first FET is connected between a corresponding input terminal and an output terminal in such a manner that an inherent diode of the FET is connected in a f... | 07/16/2002 |
| 6388474 | Semiconductor integrated circuit For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, P... | 05/14/2002 |
| 6313666 | Logic circuit including combined pass transistor and CMOS circuit and a method of synthesizing the logic circuit In order to produce a logic circuit excellent in circuit characteristics which are area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function, an... | 11/06/2001 |
| 6310489 | Method to reduce wire-or glitch in high performance bus design to improve bus performance A system and method of reducing wire-or glitch to improve bus speeds. In a system that supports wire-or functions, the rise time of the wave created by the off-going driver is controlled. The off-going wave is forced to climb gradually such that one propa... | 10/30/2001 |
| 6297669 | Low-technology inexpensive logic module system A system of logic modules providing AND, OR and NOT logical elements most useful in education and entertainment situations where it is important to avoid excessive costs and where speed is not a requirement utilizes electrical continuity and a lack of ele... | 10/02/2001 |
| 6262598 | Voltage level shifter A voltage level shifter comprises complementary transistors T1, T2 connected between a supply line vdd and an inverting input !IN. The gate of the transistor T1 is connected to a direct signal input IN whereas the gate of the transistor T2 receives a shif... | 07/17/2001 |
| 6259276 | Semiconductor integrated circuit For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, P... | 07/10/2001 |
| 6239619 | Method and apparatus for dynamic termination logic of data buses An apparatus for dynamic termination logic of bi-directional data buses and methods of operating the same result in bi-directional data buses with improved data transfer performance. The bi-directional data bus for wire-or data transfers comprises a first... | 05/29/2001 |
| 5804990 | Wired combinational logic circuit with pullup and pulldown devices A wired combinational logic arrangement responsive to N binary signal sources includes N circuits, one for each source. The circuits drive a common output terminal. Each circuit includes first and second devices for pulling the common terminal to first an... | 09/08/1998 |
| 5796128 | Gate array with fully wired multiplexer circuits A gate array architecture adapted for serial multiplexer-based circuits. In one embodiment, the gate array contains base cells having functional but isolated serial multiplexer circuits therein. In another embodiment, a base cell contains a single serial ... | 08/18/1998 |
| 5701094 | Logic circuits for wave pipelining A family of CFET logic circuits useful for wave-pipeline systems is described, and a method to design same. The invention uses complementary transmission gates and pull-up or pull-down transistors to achieve a family of CFET logic circuits which include A... | 12/23/1997 |
| 5621677 | Method and apparatus for precharging match output in a cascaded content addressable memory system A method and apparatus for increasing the speed of a cascaded Content Addressable Memory (CAM) system by pre-charging the system match line of the CAM system are disclosed. The CAM system has (i) a plurality of CAM chips, (ii) a separate match output circ... | 04/15/1997 |
| 5528177 | Complementary field-effect transistor logic circuits for wave pipelining A family of CFET logic circuits useful for wave-pipeline systems is described, and a method to design same. The invention uses complementary transmission gates and pull-up or pull-down transistors to achieve a family of CFET logic circuits which include A... | 06/18/1996 |
| 5488317 | Wired logic functions on FPGA's An FPGA having a plurality of logic modules with configurable output drivers (8) to enable outputs (y) of several logic modules to be wired together. The output driver (8) comprises a n-channel and a p-channel driver transistor (16, 20) which are connecte... | 01/30/1996 |
| 5408146 | High performance backplane driver circuit A driver circuit formed from CMOS material is provided for receiving an input logic signal from an internal CMOS circuit and inducing a corresponding output signal onto a terminated transmission line. The driver circuit comprises a pre-driver invertor hav... | 04/18/1995 |
| 5243227 | Fine/coarse wired-or tapped delay line The present invention is directed to a delay line for providing fine timing adjustment on subsequent edges of an input signal. The delay line comprises a plurality of delay elements for fine tuning the position in time of the timing edges of the input sig... | 09/07/1993 |
