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| Number | Title | Issue Date |
| 8049529 | Fault triggerred automatic redundancy scrubber A redundancy scrubber. The novel scrubber includes fault detection logic for detecting if a circuit has been upset and a mechanism for automatically rewriting data to the circuit when an upset is detected. In an illustrative embodiment, the scrubber corrects for ups... | 11/01/2011 |
| 7990173 | Single event upset mitigation A circuit for handling single event upsets includes a plurality of digital clock manager circuits. A plurality of counters are respectively coupled by their inputs to the outputs of the digital clock managers and a reset controller is coupled to the outputs of the c... | 08/02/2011 |
| 7965098 | Hardened current mode logic (CML) voter circuit, system and method A current mode logic voter circuit includes three two-input split NOR gates. Each two-input split NOR gate receives a corresponding pair of input signals and generates a pair of first output signals responsive to the input signals. A three input split NOR gate is co... | 06/21/2011 |
| 7859292 | Methods and circuitry for reconfigurable SEU/SET tolerance A device is disclosed in one embodiment that has multiple identical sets of programmable functional elements, programmable routing resources, and majority voters that correct errors. The voters accept a mode input for a redundancy mode and a split mode. In the redun... | 12/28/2010 |
| 7688102 | Majority voter circuits and semiconductor devices including the same A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a fir... | 03/30/2010 |
| 7424642 | Method for synchronization of a controller A system and method for reintegration of a redundant controller after occurrence of a fault is provided, comprising synchronizing outputs of a primary controller with outputs of secondary controllers. The controller is placed in a different mode of operation in whic... | 09/09/2008 |
| 7406608 | Fast and compact circuit for bus inversion A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, t... | 07/29/2008 |
| 7394285 | Circuit for driving bus A bus driving circuit includes a majority voter unit for comparing the number of logic high level bits with the number of logic low level bits among a predetermined number of bits of data; a latch unit for latching a first output signal in response to the compared r... | 07/01/2008 |
| 7375544 | Semiconductor apparatus having logic level decision circuit and inter-semiconductor apparatus signal transmission system In a signal transmission system between a plurality of semiconductor apparatuses, a logic level decision circuit deciding a logic level of an input signal in accordance with which of two reference signals a signal level of the input signal is close to, by using two ... | 05/20/2008 |
| 7298168 | Method and apparatus for error mitigation of programmable logic device configuration memory A method and apparatus to reduce the probability of programmable logic device (PLD) failure due to single event upset (SEU) of configuration memory. A first portion of configuration memory cells are initially programmed with configuration data, leaving a second port... | 11/20/2007 |
| 7288957 | Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the rou... | 10/30/2007 |
| 7283409 | Data monitoring for single event upset in a programmable logic device Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators... | 10/16/2007 |
| 7268570 | Apparatus and method for customized burn-in of cores on a multicore microprocessor integrated circuit chip An apparatus and method for providing a multi-core integrated circuit chip that reduces the cost of the package and board while optimizing performance of the cores for use with a single voltage plane. The apparatus and method of the illustrative embodiments make use... | 09/11/2007 |
| 7250786 | Method and apparatus for modular redundancy with alternative mode of operation A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of operation. Intelligent voting circuitry facilitates both modes of operation, while further enhancing the ro... | 07/31/2007 |
| 7236005 | Majority voter circuit design A method and apparatus for performing majority voting is presented. The method selects pairs of inputs, performs AND and NOR operations on each pair of inputs to determine that each pair of inputs is both high or both low, yielding a quantity of “both high” pair... | 06/26/2007 |
| 7236000 | Method and apparatus for error mitigation of programmable logic device configuration memory A method and apparatus to reduce the probability of programmable logic device (PLD) failure due to single event upset (SEU) of configuration memory. A first portion of configuration memory cells are initially programmed with configuration data, leaving a second port... | 06/26/2007 |
| 7224178 | Circuit re-synthesis and method for delay variation tolerance By adding redundant logic gates into a circuit without changing function of the whole circuit, the present invention can tolerate certain delay variations. The present invention can be applied in the IC industries to improve the yield in semiconductor manufacturing.... | 05/29/2007 |
| 7205986 | Image display device and testing method of the same It is the primary object of the present invention to provide a simple and accurate testing circuit and a testing method while occupying as small space as possible in an image display device. The testing circuit including a NAND circuit connected in series is mounted... | 04/17/2007 |
| 7190625 | Method and apparatus for data compression in memory devices A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each column of each array. The digit lines are selectively coupled to a pa... | 03/13/2007 |
| 7187204 | Circuit for inspecting semiconductor device and inspecting method It is configured by plurality of NAND circuits connected in series through a plurality of inverters, and a plurality of NOR circuits connected in series through the plurality of inverters. Each of a plurality of source signal lines provided in a pixel portion is con... | 03/06/2007 |
| 7183792 | Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same A threshold detection circuit for developing a mode trigger signal includes an input that receives an input signal. In response to the input signal having approximately an input threshold value for a triggering time, the threshold detection circuit activates the mod... | 02/27/2007 |
| 7176993 | Reflection type display device using a light shading film with a light shading material evenly dispersed throughout Among insulating layers for insulating and separating first wiring lines, second wiring lines, and pixel electrodes constituting a reflection type display device, at least one layer is made of an insulating film in which a carbon-based material or a pigment is dispe... | 02/13/2007 |
| 7173448 | Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the rou... | 02/06/2007 |
| 7136316 | Method and apparatus for data compression in memory devices A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each column of each array. The digit lines are selectively coupled to a pa... | 11/14/2006 |
| 7075328 | Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the rou... | 07/11/2006 |
| 7071725 | Data processing apparatus and logical operation apparatus A data processing apparatus comprises a plurality of input signal lines, a plurality of output signal lines and an electronic circuit. The electronic circuit inputs first data from the plurality of input signal lines and outputs second data to the plurality of outpu... | 07/04/2006 |
| 6999361 | Method and apparatus for data compression in memory devices A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each column of each array. The digit lines are selectively coupled to a pa... | 02/14/2006 |
| 6963217 | Method and apparatus for creating circuit redundancy in programmable logic devices A method for reducing circuit sensitivity to single event upsets in programmable logic devices, involves identifying single event upset sensitive gates within a single event upset sensitive sub-circuit of a programmable logic device as determined by the input enviro... | 11/08/2005 |
| 6928606 | Fault tolerant scan chain for a parallel processing system A highly robust fault tolerant scan chain is designed for scanning (and/or controlling a configuration of) a parallel processing system. The scan chain implements parallel redundant scan chains that follow physically diverse paths through the parallel processing sys... | 08/09/2005 |
| 6910173 | Word voter for redundant systems The present invention provides a word voter for redundant systems with n modules wherein each of these n modules generates a word output. The word voter receives word outputs from each of the n modules. A voter decision is generated by the word voter utilizing a wor... | 06/21/2005 |
| 6838899 | Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the rou... | 01/04/2005 |
| 6812731 | Quintuple modular redundancy for high reliability circuits implemented in programmable logic devices Structures and methods for generating high reliability designs for PLDs on which single event upsets have minimal impact. When standard triple modular redundancy (TMR) methods are used in PLDs, a single event upset can short together two module output signals and re... | 11/02/2004 |
| 6762617 | Semiconductor device having test mode entry circuit A semiconductor device has a normal operation mode and a test mode. A decision circuit determines whether the device has entered the test mode. A control circuit changes information related to the normal operation mode when a test mode has been entered. If the test ... | 07/13/2004 |
| 6720793 | Quintuple modular redundancy for high reliability circuits implemented in programmable logic devices Structures and methods for generating high reliability designs for PLDs on which single event upsets have minimal impact. When standard triple modular redundancy (TMR) methods are used in PLDS, a single event upset can short together two module output signals and re... | 04/13/2004 |
| 6637005 | Triple redundant self-scrubbing integrated circuit A fault tolerant integrated circuit employs triple redundant storage of data and continuous voting to protect the data from Single Event Upset, or SEU. The integrated circuit includes three or more registers and a majority voter. The three registers are c... | 10/21/2003 |
| 6624654 | Methods for implementing circuits in programmable logic devices to minimize the effects of single event upsets Methods for implementing a circuit in a programmable logic device (PLD) that protect the circuit from the effects of single event upsets. When routing nodes within the circuit using the interconnect lines of the PLD, two routed nodes are separated from ea... | 09/23/2003 |
| 6501294 | Neuron circuit A neuron circuit that can be served as a building block for a neural network implemented in an integrated circuit is disclosed. The neuron circuit includes a synapse circuit block and a neuron body circuit block. The synapse circuit block has three transi... | 12/31/2002 |
| 6480019 | Multiple voted logic cell testable by a scan chain and system and method of testing the same A multiple voted integrated circuit logic cell testable by a scan chain comprises: an odd plurality of latching registers, each register having a data input for receiving a scan chain data signal and capable of latching the scan chain data signal and gene... | 11/12/2002 |
| 6417710 | Single event upset hardened latch circuit A single event upset (SEU) hardened latch circuit utilizing two cross-coupled inverters in which the voter output circuitry is fed back to the output node of the latch circuit.... | 07/09/2002 |
| 6118297 | Voting circuit and method A voting circuit (34) comprises a first variable delay (60) operable to receive a first set of signals in a clock signal and to determine a first delay based on the first set of signals. The first variable delay (60) generates a first delayed output in re... | 09/12/2000 |
