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| Number | Title | Issue Date |
| 7598773 | Radiation hardened logic circuits A radiation hardened inverter includes first and second electrical paths between an input terminal and an output terminal. A first PFET is disposed in the first electrical path, and a bipolar junction transistor (BJT) is disposed in the second electrical path. The f... | 10/06/2009 |
| 7554364 | High-voltage operational amplifier input stage and method Circuitry for preventing damage to differentially coupled input JFETs in an integrated circuit amplifier includes first (J2) and second (J4) differentially coupled input JFETs. A first input signal (Vin+) is applied to a gate of the first input JFET (J... | 06/30/2009 |
| 7425846 | Gate driving device and flat display device employing such a gate driving device A flat display device may include a plurality of electrodes arranged in one direction, a first transistor coupled between the plurality of electrodes and a first power source for supplying a first voltage, and a gate driving circuit for supplying a driving voltage t... | 09/16/2008 |
| 7339402 | Differential amplifier with over-voltage protection and method Circuitry for preventing damage to bipolar transistors in integrated circuit amplifier circuitry during slew-limited operation includes first and second transistors, each having first, second, and third electrodes, a first one of the first and second electrodes of t... | 03/04/2008 |
| 7248082 | Sample-hold circuit A sample-hold circuit, which reduces droop and feed through and is suitable for high-speed operation while maintaining a wider freedom of design parameters, comprising a preamplifier to which an input analog signal is applied, a core section which outputs a voltage ... | 07/24/2007 |
| 7218147 | Input buffer and method of operating the same An improved input buffer providing configurable single-ended and differential signaling capability, comprising an input signal comparator, a first pad connected to one input of the comparator. An internal reference voltage source may be connected to one terminal of ... | 05/15/2007 |
| 7215170 | Low voltage logic circuit with set and/or reset functionality A low voltage logic circuit with asynchronous SET and/or RESET functions is described herein. The low voltage logic circuit may be primarily used in forming low voltage flip-flop circuits, but may also be used to form multiplexers and other logic configurations. The... | 05/08/2007 |
| 7135849 | Extremal voltage detector with high input impedance An extremal voltage detector produces an output voltage from an operational amplifier having its non-inverting input terminal connected to a first node and its inverting input terminal connected to a second node. A number of identical metal-oxide-semiconductor field... | 11/14/2006 |
| 7129750 | CMOS to PECL voltage level converter A CMOS to PECL voltage level converter includes a pad driver containing drive compensation circuitry and a feedback circuit for sensing the output drive level and providing control signals to the drive compensation circuitry for compensating for temperature and proc... | 10/31/2006 |
| 7126382 | Lower power high speed design in BiCMOS processes A low power high-speed design for integrated circuits using BiCMOS processes is disclosed. The design uses a first stage including bipolar transistor pairs configured as inputs and drivers for an output. A second CMOS stage is coupled to the first stage in a series-... | 10/24/2006 |
| 7122859 | Semiconductor device with switching element and corresponding driving circuit formed on a common semiconductor substrate, and liquid emitting apparatus that includes the semiconductor device In a semiconductor device in which a switching element for allowing a current to flow to a load and a circuit for driving the switching element are formed on a common substrate, the switching element is formed of a DMOS transistor, and the circuit for driving the sw... | 10/17/2006 |
| 7115462 | Processes providing high and low threshold p-type and n-type transistors Methods of fabricating negative-channel metal-oxide semiconductor (NMOS) devices and positive-channel metal-oxide semiconductor (PMOS) devices having complementary threshold voltages are described. Elements of lower-threshold voltage NMOS devices are formed at first... | 10/03/2006 |
| 7091751 | Low-power and low-noise comparator having inverter with decreased peak current Low-power and low-noise CDS (correlated double sampling) comparators for use with a CIS (CMOS image sensor) device are provided. A CDS comparator is constructed using one of various low-power inverters that provide decreased instantaneous transition currents at a lo... | 08/15/2006 |
| 6998881 | Semiconductor integrated circuit device In a circuit for converting an input signal Data1 of high frequency to an output signal Data4 of low frequency, a signal of the frequency band (for example, 10 GHz to 2.5 GHz) which can be processed only with a bipolar ECL circuit is processed with a b... | 02/14/2006 |
| 6518789 | Circuit configuration for converting logic levels The circuit configuration for converting logic levels has a bipolar input stage and a CMOS output stage. The bipolar input stage is equipped to process ECL and CML logic levels. The CMOS-logic output stage is equipped to supply trailing CMOS gates having ... | 02/11/2003 |
| 6388473 | Logic product circuit A logic product circuit having a plurality of transistors arranged in a matrix; a plurality of input terminals; and a single output terminal. The transistors in each column are connected in a line, forming a transistor array, the transistor arrays are con... | 05/14/2002 |
| 6225829 | device signature generator A circuit (100) for generating configurable device signatures is disclosed. The circuit (100) includes a combinatorial logic section (102) that receives a number of information signals, and according to the logic of the information signals, activates one ... | 05/01/2001 |
| 6084435 | Logic circuit A logic circuit contains a first transistor with a logic signal supplied to the base and having its collector connected to an output node. A second transistor has a collector connected to the emitter of the first transistor and an emitter connected to a r... | 07/04/2000 |
| 6031392 | TTL input stage for negative supply systems A TTL input stage for negative supply voltage systems is described herein which obviates the need for a positive supply and a level shifter. In one embodiment, a first JFET current source, the emitter/collector of a PNP bipolar transistor, and a second JF... | 02/29/2000 |
| 5869985 | Low voltage input buffer A differential input buffer operable at power supply voltages below 3.0 V comprises first and second field effect transistors connected between a power supply and a current source as a differential pair in receiving input and input bar signals. Using enha... | 02/09/1999 |
| 5850155 | BIMOS logic circuit directly controllable by a CMOS block formed on same IC chip A single chip IC includes a bipolar logic, a complementary metal-oxide semiconductor (CMOS) logic, and a level translator which interfaces the bipolar logic with the CMOS logic. The single chip IC comprises a MOS transistor logic, provided in the bipolar ... | 12/15/1998 |
| 5818259 | Low voltage logic circuit A BiCMOS logic circuit having greater drive and speed at low voltage is provided. The logic circuit includes a switching device which allows the pull-down device of the logic circuit to be driven directly by an input signal without first having to switch ... | 10/06/1998 |
| 5469084 | BiCMOS output driver A novel, high-performance BiCMOS Output Driver. The Output Driver comprises a first pull-up means for pulling high the output of the Output Driver and a pull-down means for pulling low the output of the Output Driver. The first pull-up means includes a bi... | 11/21/1995 |
| 5457413 | BiMIS logic circuit A BiMIS circuit has first and second input terminals; first and second output terminals; a first bipolar transistor having a collector receiving a first potential, an emitter connected to the first output terminal, and a base connected to the second outpu... | 10/10/1995 |
| 5434517 | ECL output buffer with a MOS transistor used for tristate enable An ECL output buffer circuit is constituted by an output buffer circuit main portion and its control circuit. In the output buffer circuit main portion, an output from a differential switch is input to the base of a bipolar transistor (emitter follower). ... | 07/18/1995 |
| 5430398 | BiCMOS buffer circuit A BiCMOS non-inverting buffer circuit (40) with small fan-in capacitance and excellent bipolar output drive. The circuit is ideal for buffering CMOS logic gates from excessive fan-out loads. The circuit also is less complex and more silicon efficient than... | 07/04/1995 |
| 5422848 | ECL-to-CMOS buffer having a single-sided delay An ECL-to-CMOS buffer having a single-sided delay comprises an ECL logic gate, a level converter, a plurality of series connected inverters, and a NOR gate. The ECL logic gate receives an ECL level input signal, and provides complementary intermediate lev... | 06/06/1995 |
| 5382843 | One or two transistor logic with temperature compensation and minimized supply voltage The logic ensures a smallest achievable propagation delay, lowest achievable supply voltage and low power consumption. Silicon or GaAs can be used. The gain of each gate is preferably low. A local supply voltage E depends on temperature and is provided fo... | 01/17/1995 |
| 5371421 | Low power BiMOS amplifier and ECL-CMOS level converter A BiMOS amplifier device includes one stage which can function as both a level-shift and buffer stage and an amplifier stage. The amplifier includes first and second bipolar transistors having their bases connected to first and second input terminals, res... | 12/06/1994 |
| 5365123 | Semiconductor logic circuits with diodes and amplitude limiter A CMOS gate circuit constituting the input stage of a semiconductor logic circuit includes a p channel MOS transistor supplied with current from a first power supply potential Vdd for charging an output signal line to a high level potential, a diode provi... | 11/15/1994 |
| 5361004 | TTL-CMOS output stage for an integrated circuit A TTL-CMOS output stage for an integrated circuit includes a bipolar transistor and a MOS transistor series connected between the power supply and ground, their common point forming the output terminal of the TTL-CMOS output stage. A first switching contr... | 11/01/1994 |
| 5357154 | Level converter circuit for converting ECL-level input signals A level converter circuit, in which a bipolar transistor for raising an output voltage is switched on or off by a logical-BiMIS construction, and a MIS transistor for falling the output voltage is also switched on or off by a logic circuit and a charge di... | 10/18/1994 |
| 5352942 | Gate array semiconductor circuit device, input circuit, output circuit and voltage lowering circuit A gate array chip is supplied with an operation voltage of 5V. A logic circuit formed of gate arrays in a chip is operated on an operation voltage of 3.3V. The potential of 3.3V is derived by lowering the potential of 5V by use of a voltage lowering circu... | 10/04/1994 |
| 5333282 | Semiconductor integrated circuit device with at least one bipolar transistor arranged to provide a direct connection between a plurality of MOSFETs In a semiconductor integrated circuit device having at least two logic blocks each including at least two logic units each having a number of MOS FET's integrated therein, bipolar transistors for driving the MOS FET's are selectively arranged between the ... | 07/26/1994 |
| 5323070 | Output buffer circuit having output bouncing controlled circuits A first output buffer having a large current driving capability and a second output buffer having a small current driving capability are connected in parallel between an input terminal and an external lead. The first and second output buffers each include... | 06/21/1994 |
| 5313116 | Semiconductor integrated circuit device having bipolar transistor and field effect transistor A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5 V. The logic circuit includes a bipolar... | 05/17/1994 |
| 5311077 | Power supply, temperature, and load capacitance compensating, controlled slew rate output buffer A controlled slew rate output buffer has an input stage that generates a charging current in response to the rising edge of an input signal and that generates a discharging current in response to the falling edge of the input signal so that both the charg... | 05/10/1994 |
| 5311078 | Logic circuit and semiconductor device In order to obtain a logic circuit capable of performing a high-speed operation, respective gates of a P-channel MOSFET (1) and an N-channel MOSFET (2) are connected to an input node (6) in common, and ends of resistors (12, 13) are connected to respectiv... | 05/10/1994 |
| 5309039 | Power supply dependent input buffer A power supply dependent input buffer (20) having a differential amplifier (22), emitter-follower transistors (29 and 32), level shifting resistors (30 and 33), and power supply dependent current sources (31 and 34) receives an ECL input signal referenced... | 05/03/1994 |
| 5309042 | Full swing BiCMOS amplifier A BiCMOS amplifier provides full swing with fast transitions from Vdd to Vss and from Vss to Vdd, and therefore has important applications in low voltage BiCMOS VLSI circuits. A bipolar totem pole output transis... | 05/03/1994 |
