Class 326/108 - CMOS

Subclass of Class 326 - Electronic digital logic circuitry
Definition: Subject matter wherein the logic function unit includes
No. of patents: 208
Last issue date: 06/28/2011

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Number	Title	Issue Date
7969201	Decoder circuit A decoder circuit that can prevent the delay of decoder output includes a switch that is put into an ON state when a node A of an NMOS region is not an output channel of a selected gradation voltage. The switch is connected to the node A. Thus, a voltage raised by e...	06/28/2011
7423450	Techniques for providing calibrated on-chip termination impedance Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. Th...	09/09/2008
7378879	Decoding systems and methods Systems and methods are disclosed herein for decoder applications. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a decoder that receives a plurality of input signals and partially decodes the input signals bas...	05/27/2008
7372305	Scannable dynamic logic latch circuit A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a scan pull-down logic tree that is coupled to a scan hold latch outpu...	05/13/2008
7358769	XOR circuit An XOR circuit designed in dual rail includes four shunt transistors, wherein the shunt transistors are disposed to couple an input potential at a first input or a second input with an output. ...	04/15/2008
7355435	On-chip detection of power supply vulnerabilities On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outs...	04/08/2008
7327169	Clocked inverter, NAND, NOR and shift register A threshold voltage of a transistor is fluctuated because of fluctuation in film thickness of a gate insulating film or in gate length and gate width caused by differences of used substrates or manufacturing steps. In order to solve the problem, according to the pre...	02/05/2008
7282984	Semiconductor device having an internal voltage converter, and method therefor An internal voltage converter and method is provided capable of reducing power consumption using a selective voltage reference, a semiconductor device including the internal voltage converter. A semiconductor device uses the internal voltage converter which discrimi...	10/16/2007
7279936	Logic basic cell, logic basic cell arrangement and logic device A logic basic cell, a logic basic cell arrangement, and a logic device. A logic basic cell is provided for forming a logic combination of two data signals in accordance with a logic function that can be selected by means of a plurality of logic selection elements, h...	10/09/2007
7272624	Fused booth encoder multiplexer A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results...	09/18/2007
7269212	Low-latency equalization in multi-level, multi-line communication systems Low-latency equalization mechanisms for multi-PAM communication systems are disclosed that reduce delay and complexity in signal correction mechanisms. The equalization mechanisms tap into input signals for a multi-PAM signal driver, and compensate for attenuation a...	09/11/2007
7230477	Semiconductor integrated circuit device A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a ...	06/12/2007
7227806	High speed wordline decoder for driving a long wordline A method and apparatus for improving the performance of a memory wordline decoder is disclosed. A decoder latch is attached to an inverter which drives the wordline. Additionally, a voltage pump can supply operating voltage to the inverter to assist in overdriving t...	06/05/2007
7221192	Voltage access circuit configured for outputting a selected analog voltage signal for testing external to an integrated circuit Access is provided to internal analog voltage signals on internal analog nodes of an integrated circuit, without distortion of the internal analog voltage signals. An integrated circuit includes a voltage access circuit having buffered multiplexer circuits in proxim...	05/22/2007
7221185	Method and apparatus for memory block initialization In one aspect of the invention, a circuit for generating addresses for memory initialization within a programmable logic device (PLD) is provided. The circuit includes input registers, which are loaded and unloaded with data triggered by the edge of a clock. The cir...	05/22/2007
7212062	Power supply noise insensitive multiplexer CMOS circuitry used to multiplex between data inputs suffers from high sensitivity to power supply noise, resulting in delay variations. By utilizing current controlled inverters in a multiplexer structure, power supply insensitivity can be achieved with either of t...	05/01/2007
7199616	Method and apparatus to generate break before make signals for high speed TTL driver A driver includes, in part, a delay chain having disposed therein a multitude of accessible nodes, and a control logic coupled to the various nodes of the delay chain to generate the signals applied to the gate terminals of the PMOS and NMOS transistors disposed in ...	04/03/2007
7181966	Physical quantity sensor and method for manufacturing the same A capacitance type humidity sensor includes: a detection substrate including a detection portion on a first side of the detection substrate; and a circuit board including a circuit portion. The detection portion detects humidity on the basis of capacitance change of...	02/27/2007
7176725	Fast pulse powered NOR decode apparatus for semiconductor devices A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and th...	02/13/2007
7173874	Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided. The memory array includes (r·s·t) memory locations with the memory array organized as a first memory sub...	02/06/2007
7170320	Fast pulse powered NOR decode apparatus with pulse stretching and redundancy steering A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and th...	01/30/2007
7145364	Self-bypassing voltage level translator circuit A voltage level translator circuit is selectively operable in one of at least two modes in response to a control signal. In a first mode, the voltage level translator circuit is operative to translate an input signal referenced to a first source providing a first vo...	12/05/2006
7138833	Selector circuit A plurality of conduction control circuits controls conduction of input signals. A logical operation circuit receives output signals from each of the conduction control circuits via a plurality of signal paths, and performs a logical operation on each of the output ...	11/21/2006
7129755	High-fanin static multiplexer An improved high-fanin multiplexer that is highly-scalable, fast and area-efficient. In one embodiment of the present invention, multiple logic “legs” are attached to a common output line. Each leg comprises one pMOS pull-up transistor and one nMOS pull-down tra...	10/31/2006
7126394	History-based slew rate control to reduce intersymbol interference In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were transmitted over the line. If the bit on the line has been static for several clock cycles, the slew rate wil...	10/24/2006
7126408	Method and apparatus for receiving high-speed signals with low latency An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time inter...	10/24/2006
7109758	System and method for reducing short circuit current in a buffer A system for reducing a transition short circuit current in an inverter circuit includes a first inverter and a variable resistor set. The first inverter includes a first output node, a first PMOS device, and a first NMOS device. The variable resistor set biases the...	09/19/2006
7093145	Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals A current controller for a multi-level current mode driver. The current controller includes a multi-level voltage reference and at least one source calibration signal. A comparator is coupled by a coupling network to the multi-level voltage reference and the at leas...	08/15/2006
7075850	Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided. The memory array includes (r•s•t) memory locations with the memory array organized as a first memory s...	07/11/2006
7072415	Method and apparatus for generating multi-level reference voltage in systems using equalization or crosstalk cancellation A system and method are shown for generation of at least one reference voltage level in a bus system. A reference voltage generator on a current driver includes at least one reference voltage level, at least one control signal, and an active device. The active devic...	07/04/2006
7068563	Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided. The memory array includes (r•s•t) memory locations with the memory array organized as a first memory s...	06/27/2006
7053661	Impedance-matched output driver circuits having enhanced predriver control Impedance-matched output driver circuits utilize predriver circuits with analog control to provide enhanced operating characteristics. This analog control may be provided by an analog loop containing differential amplifiers that set the resolution limit of the outpu...	05/30/2006
7053663	Dynamic gate with conditional keeper for soft error rate reduction A dynamic logic gate with a conditional keeper, the conditional keeper comprising a pMOSFET pull-up that switches ON only after the dynamic logic gate completes an evaluation so as to avoid contention with the pull-down network. By sizing the conditional keeper to b...	05/30/2006
7049851	Decoder circuit A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode...	05/23/2006
7038486	Semiconductor integrated circuit device A plurality of sets of circuits are provided, each of which generates an impedance code through the use of an impedance control circuit in association with a resistive element connected to an external terminal, and each of which varies the impedance in accordance wi...	05/02/2006
6995600	Fast and wire multiplexing circuits An apparatus for a multiplexor circuit includes a passgate circuit coupled to receive input signals and corresponding select signals comprising a subset of the input signals and select signals received by the multiplexor. The apparatus also includes a default circui...	02/07/2006
6965262	Method and apparatus for receiving high speed signals with low latency An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time inter...	11/15/2005
6954401	Semiconductor memory device integrating source-coupled-logic (SCL) circuit into an address buffer and a decoder It is an object of the invention to provide a circuit configuration wherein a decoder control signal Φ2 is rendered unnecessary between an address buffer control signal Φ1 and the decoder control signal Φ2, thereby implementing speed-up in op...	10/11/2005
6937072	Driver circuit and method for operating a driver circuit The invention relates to a driver circuit (10) for integrated circuits comprising at least one input node (11) for an input signal and at least one output node (12) for an output signal. One or several, preferably two partial drivers (20, 30	08/30/2005
6937538	Asynchronously resettable decoder for a semiconductor memory A hierarchical memory structure having memory cells, and sense amplifiers and decoders coupled with the memory cells to form first tier memory module, and subsequent tiers being formed by having (n−1)-tier memory modules, which are coupled with (n)-tier sense ampl...	08/30/2005

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Class 326/108 - CMOS