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| Number | Title | Issue Date |
| 7368969 | Level shift circuit and semiconductor device A level shift circuit including a capacitor, a charge control circuit, and a limiting circuit. The charge control circuit is connected to the capacitor to provide the voltage of a high potential power supply to the capacitor and to control the charging of the capaci... | 05/06/2008 |
| 7187587 | Programmable memory address and decode circuits with low tunnel barrier interpoly insulators Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the ou... | 03/06/2007 |
| 7164294 | Method for forming programmable logic arrays using vertical gate transistors One aspect disclosed herein relates to a method for forming a programmable logic array. Various embodiments of the method include forming a first logic plane and a second logic plane, each including a plurality of logic cells interconnected to implement a logical fu... | 01/16/2007 |
| 6977410 | Test mode decoder in a flash memory Embodiments of the present invention include an interface circuit to put an integrated circuit into a test mode and a decoder to decode one or more commands provided to the integrated circuit. The decoder includes sub-circuits, and each sub-circuit has a number of t... | 12/20/2005 |
| 6917239 | Level shift circuit and semiconductor device A level shift circuit including a capacitor, a charge control circuit, and a limiting circuit. The charge control circuit is connected to the capacitor to provide the voltage of a high potential power supply to the capacitor and to control the charging of the capaci... | 07/12/2005 |
| 6864721 | Decoder circuit A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode... | 03/08/2005 |
| 6759873 | Reverse biasing logic circuit A reverse biasing logic circuit is disclosed for limiting standby leakage electric current losses during circuit operation. The circuit includes a logic function circuit having one or more logic transistors that receive an input and perform a logic function operatio... | 07/06/2004 |
| 6653998 | LCD driver for layout and power savings A driver circuit for use in driving displays has an input receiving a digital input data having n bits for selecting one of a plurality of voltage levels for driving the circuit. The circuit also has an output, a plurality of digital signal lines coupled ... | 11/25/2003 |
| 6593776 | Method and apparatus for low power domino decoding A decoder includes multiple decode gates, each to provide one bit of a decoded output signal. At least two of the decode gates share a transistor. According to one aspect, each of the multiple decode gates is a skewed gate.... | 07/15/2003 |
| 6496035 | Integrated circuit approach, with a serpentine conductor track for circuit configuration selection An integrated circuit includes a serpentine conductor track extending through a plurality of conductor layers and having ends coupled to first and second circuit elements, the ends being in opposing outermost ones of the conductor layers. The serpentine c... | 12/17/2002 |
| 6201416 | Field effect transistor logic circuit with reduced power consumption There is disclosed a field effect transistor logic circuit having an output terminal to be connected to a gate of an input field effect transistor in a next stage field effect transistor logic circuit. The field effect transistor logic circuit includes a ... | 03/13/2001 |
| 5848013 | Row decoding circuit for semiconductor non-volatile electrically programmable memory and corresponding method The invention relates to a row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of the type which includes a matrix of memory cells laid out as cell rows and columns and is divided into sectors, said... | 12/08/1998 |
| 5801551 | Depletion mode pass gates with controlling decoder and negative power supply for a programmable logic device Depletion mode pass gates utilized in a PLD to enable a gate voltage of Vcc to be applied for turn off, as opposed to a higher voltage required for enhancement type devices. With Vcc applied for turn off, gate oxide stress is reduced and chip reliability ... | 09/01/1998 |
| 5504439 | I/O interface cell for use with optional pad In a programmable integrated circuit device, a pad interface structure is provided in which the number of pads connected to the interface structure is selectively changed without redesigning the interface structure or redesigning the chip interior.... | 04/02/1996 |
| 5187394 | Configurable row decoder driver circuit A configurable decode circuit for decoding in a block architected SRAM. The configurable decode circuit comprising a decode circuit (10) which decodes through a process of deselection, a first buffer circuit (12) for buffering decode circuit (10), a delay... | 02/16/1993 |
| 5056062 | Method of operating an EPROM including delaying and boosting steps A method of operating an EPROM which has a word line, a predecode circuit having an ou tput terminal and a transistor having a first electrode connected to the output terminal of the predecode circuit, a second electrode connected to a word line and a con... | 10/08/1991 |
| 4727267 | Clocked buffer circuit The present invention is especially directed towards an improved clocked buffer circuit that will clock, decode, repeat and invert an input signal. The clocked buffer circuit uses a clocked latch coupled to a decode circuit such that not only will the app... | 02/23/1988 |
| 4700086 | Consistent precharge circuit for cascode voltage switch logic A precharge circuit for a cascode voltage switch in which at the beginning of the precharge phase the output state is memorized and the output is isolated from the precharging points. Both the positive and negative ends of the discharge paths are precharg... | 10/13/1987 |
| 4678941 | Boost word-line clock and decoder-driver circuits in semiconductor memories A CMOS boost word-line clock and decoder-driver circuit which can be used for CMOS DRAM's with substrate bias in addition to VDD supply. A boost word-line clock circuit including simple CMOS inverters is used for the word-line boost and the possible volta... | 07/07/1987 |
| 4672240 | Programmable redundancy circuit A memory redundancy circuit is described incorporating a sequential row or column counter associated with a plurality of programmable row or column decoders. The sequential row counter includes a sequence circuit for each programmable row decoder.The sequ... | 06/09/1987 |
| 4651031 | Address decoder circuit An address decoder circuit of the present invention forms a word line selection signal by entering an m-bit address signal by dividing it into two groups of i bits and (m-i) bits. The decoder output from the i-bit signal is inputted to the gate of a first... | 03/17/1987 |
| 4631425 | Logic gate circuit having P- and N- channel transistors coupled in parallel A logic circuit on a semiconductor chip having a decoding or a selecting function has at least two input transistors coupled in parallel between an output node and a reference point. Input signals are applied to the input transistors, and an output is der... | 12/23/1986 |
| 4620116 | Decoder circuit with setting function of an output level A decoder circuit for use in a semiconductor member device or the like as a first metal insulator semiconductor field effect transistor (MISFET) acting as a load element, a plurality of parallel-connected MISFETs controlled by the output signals of an add... | 10/28/1986 |
| 4618784 | High-performance, high-density CMOS decoder/driver circuit A decoder/driver circuit for a semiconductor momory having a A1 to AN (true) and A1 to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A .PHI.PC line is included for receiving a .PHI.PC prech... | 10/21/1986 |
| 4612462 | Logic circuit having voltage booster When an input signal to be supplied to a signal input end becomes high, a voltage corresponding to the signal of logic level "1" is boosted by a voltage booster, and a boosted voltage appears at a signal output end. During this operation, a switching circ... | 09/16/1986 |
| 4611131 | Low power decoder-driver circuit A memory decoder wherein a power-up device is interposed between a NOR decoder and ground (VSS), rather than between the decoder and VDD. Preferably the signal to the power-up transistor is itself decoded, so that the power-consuming NOR circuits are inac... | 09/09/1986 |
| 4563598 | Low power consuming decoder circuit for a semiconductor memory device The present invention is directed to a decoder circuit for a semiconductor memory device including a logic circuit for receiving an address signal as an input thereto and selecting an address in response thereto and a load in the logic circuit. The load c... | 01/07/1986 |
| 4563599 | Circuit for address transition detection A circuit uses a pair of transistors in series to provide an output pulse which indicates an address transition has occurred. A duration of joint conductivity of the pair of transistors determines the duration of the output pulse. For an address transitio... | 01/07/1986 |
| 4554469 | Static bootstrap semiconductor drive circuit A semiconductor circuit has a static bootstrap circuit, which includes a first MOS transistor with an input signal supplied to the gate and having the current path connected between a voltage source terminal and a node, a second MOS transistor having the ... | 11/19/1985 |
| 4542485 | Semiconductor integrated circuit A semiconductor integrated circuit comprises a first MOS transistor connected at the drain to a power source terminal of a high potential power source and supplied at the gate with a predetermined voltage, a logic circuit including MOS transistors provide... | 09/17/1985 |
| 4520463 | Memory circuit A memory circuit having an improved address decoder which is operable with a low power consumption and can be fabricated at a high-integration is disclosed. The memory comprises a logic means for decoding a part of address signals provided for a plurality... | 05/28/1985 |
| 4509148 | Semiconductor memory device A semiconductor memory circuit includes a plurality of semiconductor memory areas, a plurality of data lines connected to the memory areas for the transfer of data with respect thereto, a plurality of word lines for transmitting access signals to the memo... | 04/02/1985 |
| 4500799 | Bootstrap driver circuits for an MOS memory A bootstrap driver circuit is used asynchronously in a static RAM. A capacitor is coupled between second and third nodes, and a charge pump is coupled to provide charge to the second node. Address bits can be applied to the gates of respective transistors... | 02/19/1985 |
| 4471240 | Power-saving decoder for memories A decoder for memories improves speed and reduces power consumption by gating the power to a parallel decoder to provide a signal to a bootstrap circuit for providing an enable signal at essentially the voltage present at a positive power supply terminal.... | 09/11/1984 |
| 4446386 | MOS Decoder circuit using phase clocking for reducing the power consumption In a decoder circuit in which a transistor for reducing power use, which is supplied at its gate with a first control signal, is connected in series with a logical gate composed of a load transistor and a plurality of transistors which are respectively su... | 05/01/1984 |
| 4348596 | Signal comparison circuit The circuit compensates for the difference in the source impedances of signal and reference generating circuits whose outputs are coupled to a sense circuit which loads (draws current from) the signal and reference generating circuits. The signal generati... | 09/07/1982 |
| 4289982 | Apparatus for programming a dynamic EPROM An insulated-gate field-effect-transistor (IGFET) quasi-static decoder for programming an electronically-programmable read-only memory (EPROM) applies to the floating gate of selected memory devices a programming voltage. Prior to selection, each row and ... | 09/15/1981 |
| 4274147 | Static read only memory A static read only memory fabricated with field effect transistors of either the depletion type or the enhancement type connected in series. The read only memory includes a compact sensing circuit for detecting relatively small voltage swings at each node... | 06/16/1981 |
| 4103189 | MOS Buffer circuit An MOS buffer circuit which may be employed as part of a electrically programmable read-only memory or other MOS integrated circuit is described. The buffer may be "powered down" when the memory is in a standby mode. Low threshold (zero threshold) voltage... | 07/25/1978 |
| 4025799 | Decoder structure for a folded logic array This specification describes a decoder for use in a programmable logic array (PLA) of the type having opposite ends of input lines of the array connected to outputs of different decoders. Instead of using the outputs of two two-bit decoders to drive four ... | 05/24/1977 |
