Did You Know...
...that the Eveready Battery began as an invention called the "electric flowerpot," which was a tube with a battery and light bulb inside? The idea was to fasten this gizmo to the side of a flowerpot so it would illuminate the flowers from the bottom. The idea died on the vine and the businessman who licensed the flower pot, Conrad Huber, was left with a pile of useless tubes -- until he found a way to market them as batteries to light the world!
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| Number | Title | Issue Date |
| 7656197 | Decoder circuit The decoder circuit includes: a power supply control circuit for supplying a first voltage; first and second transistors connected in series between the power supply control circuit and a first reference node; and third and fourth transistors connected between a con... | 02/02/2010 |
| 7486113 | Decoder circuit The decoder circuit includes: a power supply control circuit for supplying a first voltage; first and second transistors connected in series between the power supply control circuit and a first reference node; and third and fourth transistors connected between a con... | 02/03/2009 |
| 7411424 | Programmable logic function generator using non-volatile programmable memory switches Methods and apparatus are disclosed to implement programmable logic generators that provide the advantages of compatible look-up tables (LUTs) while utilizing less silicon real estate and power for the same number of functions. The disclosed methods and apparatus em... | 08/12/2008 |
| 7359216 | Small-frame computer with overlapping add-in cards A computer module for electrically coupling a motherboard with add-in cards comprises risers connected to the motherboard and oriented facing toward each other, where the risers are connected to the add-in cards at different elevations above the motherboard, so that... | 04/15/2008 |
| 7355435 | On-chip detection of power supply vulnerabilities On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outs... | 04/08/2008 |
| 7321530 | Decoder circuit, and photo-detecting amplifier circuit and optical pickup including the decoder circuit for disk recording/reproducing apparatus A decoder circuit of the present invention, mounted on an integrated circuit, decodes input voltage Vin supplied to a single external input terminal into three or more control outputs, and an object of the present invention is to reduce the size of a chip. The foreg... | 01/22/2008 |
| 7295481 | Power saving by disabling cyclic bitline precharge A method and system of accessing memory cells within a dynamic hardware memory block operated with a bitline precharge circuit, in which differential read/write access operations are performed by activating complementary bitlines. A reduction in power dissipation is... | 11/13/2007 |
| 7263563 | Multi-bus driver apparatus and method for driving a plurality of buses A bus driving method and apparatus for driving a plurality of buses including a control logic for generating and outputting control signals and bus selection signals, a byte rotator for dividing data from a data source into a data unit, and changing a sequence of th... | 08/28/2007 |
| 7251183 | Static random access memory having a memory cell operating voltage larger than an operating voltage of a peripheral circuit A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage n... | 07/31/2007 |
| 7245158 | Circuit wiring layout in semiconductor memory device A circuit wiring layout in a semiconductor memory device comprises first and second p-type MOS transistors having channels connected to each other in series, and first and second n-type MOS transistors having sources connected in parallel to a drain of the second p-... | 07/17/2007 |
| 7242634 | Pseudo-dynamic word-line driver In certain embodiments, the present invention is a word-line driver for an address decoder that decodes a multi-bit address to enable access to a row of circuit elements such as memory cells in a block of memory implemented in a dedicated memory device or as part of... | 07/10/2007 |
| 7230453 | Output buffer providing multiple voltages The present invention provides an output buffer providing multiple voltages including an arrangement of bootstrapping capacitors, and a charge replenishing mechanism which provides continuous pulses to the arrangement of bootstrapping capacitors, thereby, maintainin... | 06/12/2007 |
| 7221185 | Method and apparatus for memory block initialization In one aspect of the invention, a circuit for generating addresses for memory initialization within a programmable logic device (PLD) is provided. The circuit includes input registers, which are loaded and unloaded with data triggered by the edge of a clock. The cir... | 05/22/2007 |
| 7221192 | Voltage access circuit configured for outputting a selected analog voltage signal for testing external to an integrated circuit Access is provided to internal analog voltage signals on internal analog nodes of an integrated circuit, without distortion of the internal analog voltage signals. An integrated circuit includes a voltage access circuit having buffered multiplexer circuits in proxim... | 05/22/2007 |
| 7212062 | Power supply noise insensitive multiplexer CMOS circuitry used to multiplex between data inputs suffers from high sensitivity to power supply noise, resulting in delay variations. By utilizing current controlled inverters in a multiplexer structure, power supply insensitivity can be achieved with either of t... | 05/01/2007 |
| 7210108 | Structure of power supply path utilized in design of integrated circuit According to a method of designing an integrated circuit, a plurality of outgoing lines branch off from each of main lines of respective power supply paths on the sides of VDD and VSS, and the pitches between adjacent outgoing lines of the plurality of outgoing line... | 04/24/2007 |
| 7203243 | Line driver with reduced power consumption A means for reducing the power consumption of the transmitter by storing the recent history of the transmitted data using a string of gates with taps from the string taken at points determined by the propagation delay of each gate and controlling driving transistors... | 04/10/2007 |
| 7199618 | Logic circuit arrangement A logic circuit arrangement including at least two data signal inputs, at which at least two data signals are provided, a first signal path coupled to the data signal inputs, and having a plurality of transistors of a first conduction type, and a plurality of contro... | 04/03/2007 |
| 7177182 | Rewriteable electronic fuses Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predet... | 02/13/2007 |
| 7161404 | Single event upset hardened latch A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the... | 01/09/2007 |
| 7161389 | Ratioed logic circuits with contention interrupt A ratioed logic gate includes a contention interrupt circuit. The ratioed logic gate includes a pull up network coupled to a pull down network. Multiple inputs are coupled to turn the pull down and pull up networks on and off. An output is coupled to apply a logical... | 01/09/2007 |
| 7157958 | Reduced voltage pre-charge multiplexer An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which is pre-charged to a voltage less than a system voltage. Each pu... | 01/02/2007 |
| 7145370 | High-voltage switches in single-well CMOS processes Circuits are provided for high-voltage switching in single-well CMOS processes. ... | 12/05/2006 |
| 7129755 | High-fanin static multiplexer An improved high-fanin multiplexer that is highly-scalable, fast and area-efficient. In one embodiment of the present invention, multiple logic “legs” are attached to a common output line. Each leg comprises one pMOS pull-up transistor and one nMOS pull-down tra... | 10/31/2006 |
| 7126398 | Method and an apparatus to generate static logic level output A method and an apparatus to generate static logic level outputs without a direct connection from a MOS transistor gate to either a power supply or ground supply are described. The apparatus may include a first circuit comprising a static logic level output. The app... | 10/24/2006 |
| 7120061 | Method and apparatus for a dual power supply to embedded non-volatile memory A charge pump is configured to receive an external voltage level and generate a high voltage level, wherein the high voltage level is higher than the external voltage level. A memory control circuit is configured to receive the external voltage level and the high vo... | 10/10/2006 |
| 7113587 | Method and apparatus for non-disruptive telecommunication loop condition determination The invention provides a low cost, simple, circuit for detecting the condition of a telephone line. ... | 09/26/2006 |
| 7095252 | Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates The present invention relates to dynamic hardware logic of computer processors. In particular, it relates to a method and respective system for operating a dynamic logic circuit implementing some predetermined logic function with reduced charge sharing. In order to ... | 08/22/2006 |
| 7093045 | Method and apparatus for bus arbitration capable of effectively altering a priority order A bus arbitration apparatus includes a storage, a priority order determiner, and an arbitrator. The storage stores a plurality of selection signals for specifying a priority order against a number N of requests. The priority order determiner causes the storage to ou... | 08/15/2006 |
| 7088139 | Low power tri-level decoder circuit A tri-level decoder circuit includes a first decoder circuit and a second decoder circuit. The first decoder circuit is configured to compare an input voltage to a first threshold, and the second decoder circuit is configured to compare the input voltage to a second... | 08/08/2006 |
| 7068069 | Control circuit and reconfigurable logic block A control circuit for providing a control signal to build a logic circuit includes a latch circuit including first and second inverted logic gates; a first variable resistive memory provided between an output of the first inverted logic gate and an input of the seco... | 06/27/2006 |
| 7061275 | Field programmable gate array A field programmable gate array (FPGA) having hierarchical interconnect structure is disclosed. The FPGA includes logic heads that have signals routed therebetween by the interconnect structure. Each logic head includes a plurality of cascadable logic blocks that ca... | 06/13/2006 |
| 7049851 | Decoder circuit A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode... | 05/23/2006 |
| 7042251 | Multi-function differential logic gate A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be... | 05/09/2006 |
| 7042779 | Method and apparatus for reducing leakage current in a read only memory device using pre-charged sub-arrays A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by precharging only a portion of the columns in a read only memory array during a given read cycle. The portion of the columns that are precharg... | 05/09/2006 |
| 7012487 | Transconductance device employing native MOS transistors A system on chip such as a radio receiver has reduced suceptibility to voltages in the bulk silicon by using gyrator elements in the receiver with each gyrator element including a plurality of current sources interconnected to provide output transconductance voltage... | 03/14/2006 |
| 6998878 | Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit includes a semiconductor logic circuit in which the numb... | 02/14/2006 |
| 6972599 | Pseudo CMOS dynamic logic with delayed clocks Structures and methods for pseudo-CMOS dynamic logic with delayed clocks are provided. A pseudo-CMOS dynamic logic circuit with delayed clocks includes a dynamic pseudo-nMOS logic gate and a dynamic pseudo-pMOS logic gate coupled thereto. The dynamic pseudo-nMOS log... | 12/06/2005 |
| 6963227 | Apparatus and method for precharging and discharging a domino circuit A domino circuit configuration includes a precharge transistor coupled to a discharge transistor, wherein the precharge transistor and the discharge transistor are not on simultaneously. ... | 11/08/2005 |
| 6960935 | Method and apparatus for cascade programming a chain of cores in an embedded environment A system for clearing and programming the memory of an FPGA IC, when the IC is comprised of a plurality of cores. The system clears the memory of the of cores. The system then sequentially verifies completion of clearing memory of each core. The system then provides... | 11/01/2005 |
