Mountable Printable Placard With Headband
A resilient headband in a shape for being mounted on the head of the user. The headband is equipped with a longitudinal slotted member for holding a placard.
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| Number | Title | Issue Date |
| 7982505 | Logic circuit, address decoder circuit and semiconductor memory Disclosed is a logic circuit includes a first NAND gate that receives a first pulse signal and a first selection signal, a first inverter gate that inverts an output signal of the first NAND gate to output a resulting signal, a second NAND gate that receives a secon... | 07/19/2011 |
| 7969200 | Decoder circuit A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate a... | 06/28/2011 |
| 7928771 | Drive signal output circuit and multi-chip package Input signals from a signal input terminal are input to a logic circuit, and a control signal corresponding to states of the input signals is output. The control signal is supplied to an output circuit, a plurality of transistors are controlled, and a drive signal i... | 04/19/2011 |
| 7872502 | Defect-and-failure-tolerant demultiplexer using series replication and error-control encoding One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, e... | 01/18/2011 |
| 7863938 | Address decoder and method for setting an address An address decoder that sets an address of a module connected to a bus includes a level comparator, an edge detector, and an output decoder. The level comparator compares an SDA signal, which is input to an SDA terminal, with an address selection signal, which is in... | 01/04/2011 |
| 7821299 | Matrix decoder A matrix decoder is provided, which includes a plurality of first level shifters, a plurality of second level shifters, and a demultiplexer. The first level shifters and the second level shifters boost the voltages of inputted signals to the voltages required by hig... | 10/26/2010 |
| 7795922 | Decoder circuit A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate a... | 09/14/2010 |
| 7768316 | Decoder circuit, decoding method, output circuit, electro-optical device, and electronic instrument A decoder circuit comprises: first decoder section that decodes an m-bit address signal portion of an (m+n)-bit address signal; and a second decoder section that decodes an n-bit address signal portion of the (m+n)-bit address signal, the first decoder section inclu... | 08/03/2010 |
| 7719319 | Semiconductor integrated circuit In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value is selected using a selection signal, a first node N1 is L, a second node N2 of a second dynamic circuit is H, so that an output signal has an H lev... | 05/18/2010 |
| 7710158 | Command decoder and command signal generating circuit A command decoder generates a command signal based on first to fourth control signals in response to a second chip select signal generated by delaying a first chip select signal for a predetermined interval. ... | 05/04/2010 |
| 7586334 | Circuit arrangement and method for processing a dual-rail signal The present invention relates to a circuit arrangement for processing a dual-rail signal, comprising data inputs for feeding at least one dual-rail data input signal, and respective data outputs for outputting a dual-rail data output signal using the at least one du... | 09/08/2009 |
| 7557617 | Digital decoder with complementary outputs A digital decoder is provided that produces true and complementary output signals. The digital decoder may be formed from n-channel and p-channel metal-oxide-semiconductor transistors. The digital decoder produces four true outputs and four complementary outputs fro... | 07/07/2009 |
| 7545178 | Signal encoder and signal decoder A signal encoder and a signal decoder involves the signal encoder for receiving a data signal and a clock signal, including a first code output terminal and a second code output terminal. When the data signal is logic one, the signal encoder outputs a modulated sign... | 06/09/2009 |
| 7541843 | Semi-static flip-flops for RFID tags A radio frequency identification (RFID) circuit including a semi-static flip-flop having a static storage time longer than its dynamic storage time. The RFID circuit may include a timing block circuit to provide a timing block clock signal to the semi-static flip-fl... | 06/02/2009 |
| 7535260 | Logic gates, scan drivers and organic light emitting displays using the same A logic gate includes a first driver connected to a first power source, a first control transistor connected between a first node and a second power source to control a voltage of the first node, a second driver connected between a gate electrode of the first contro... | 05/19/2009 |
| 7436219 | Level shifter circuit A level shifter circuit includes: K level shifter units for receiving K input signals having a first voltage level range and outputting K output signals having a second voltage level range, wherein the second voltage level range is greater than the first voltage lev... | 10/14/2008 |
| 7417467 | Semiconductor integrated circuit In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value is selected using a selection signal, a first node N1 is L, a second node N2 of a second dynamic circuit is H, so that an output signal has an H lev... | 08/26/2008 |
| 7378879 | Decoding systems and methods Systems and methods are disclosed herein for decoder applications. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a decoder that receives a plurality of input signals and partially decodes the input signals bas... | 05/27/2008 |
| 7328377 | Error correction for programmable logic integrated circuits Systems and methods for detecting and correcting errors in programmable logic ICs are provided. In one embodiment, a scrubber periodically reads the memory cells in a programmable logic IC, detects and corrects any errors, and writes the corrected contents back into... | 02/05/2008 |
| 7327162 | Operations with logical states from a four voltage level signal Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integr... | 02/05/2008 |
| 7312627 | Decoding circuit for on die termination in semiconductor memory device and its method A decoding circuit of an on die termination (ODT) control signal for stably performing an ODT operation. The decoding circuit includes: a latch unit for receiving a plurality of input signals and for holding previous output signals of the latch unit when the plurali... | 12/25/2007 |
| 7310757 | Error detection on programmable logic resources Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compare... | 12/18/2007 |
| 7279936 | Logic basic cell, logic basic cell arrangement and logic device A logic basic cell, a logic basic cell arrangement, and a logic device. A logic basic cell is provided for forming a logic combination of two data signals in accordance with a logic function that can be selected by means of a plurality of logic selection elements, h... | 10/09/2007 |
| 7274244 | Pulse multiplexed output system A pulse multiplexed output subsystem is disclosed. In one particular exemplary embodiment, the output subsystem may comprise a plurality of pulse generators, a first pair of transistors, and a second pair of transistors, wherein each of the first pair of transistors... | 09/25/2007 |
| 7267287 | IC card An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural con... | 09/11/2007 |
| 7268591 | Decode structure with parallel rotation A memory subsystem and a method of operating therefor. The memory subsystem includes a memory array having 2n locations. The memory subsystem includes an address decoder and rotation logic each coupled to receive bits of a first address having n address b... | 09/11/2007 |
| 7266038 | Method for activating and deactivating electronic circuit units and circuit arrangement for carrying out the method The invention provides an electronic circuit arrangement having an electronic circuit module (100) constructed from one or more electronic circuit units (101a-101n), a select signal generating unit (105) for generating a sel... | 09/04/2007 |
| 7260795 | Method and apparatus for integrating a simulation log into a verification environment One embodiment of the invention provides a system that facilitates integrating a simulation log into a verification environment. The system operates by first creating the simulation log during a simulation of a register transfer language description of an integrated... | 08/21/2007 |
| 7248512 | Semiconductor memory device having controller with improved current consumption A semiconductor memory device wherein, in order to control the current consumed in a column address counter and latch block in a read operation, delay units disposed in the column address counter and latch block perform a shifting operation according to a signal CAS... | 07/24/2007 |
| 7245158 | Circuit wiring layout in semiconductor memory device A circuit wiring layout in a semiconductor memory device comprises first and second p-type MOS transistors having channels connected to each other in series, and first and second n-type MOS transistors having sources connected in parallel to a drain of the second p-... | 07/17/2007 |
| 7224052 | IC card with controller and memory chips An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural con... | 05/29/2007 |
| 7221185 | Method and apparatus for memory block initialization In one aspect of the invention, a circuit for generating addresses for memory initialization within a programmable logic device (PLD) is provided. The circuit includes input registers, which are loaded and unloaded with data triggered by the edge of a clock. The cir... | 05/22/2007 |
| 7221186 | Efficient tile layout for a programmable logic device In an integrated circuit including an array of substantially similar tiles, a tile includes a logic block and one or more columns of routing multiplexers driving interconnect lines that can be used to programmably interconnect the logic blocks. Each routing multiple... | 05/22/2007 |
| 7212062 | Power supply noise insensitive multiplexer CMOS circuitry used to multiplex between data inputs suffers from high sensitivity to power supply noise, resulting in delay variations. By utilizing current controlled inverters in a multiplexer structure, power supply insensitivity can be achieved with either of t... | 05/01/2007 |
| 7208976 | Look-up table based logic macro-cells A programmable look up table (LUT) structure that offers higher logic packing capacity over conventional LUT structures for programmable logic devices is disclosed. A programmable LUT structure comprising a first stage and one or more intermediate stages and a last ... | 04/24/2007 |
| 7199619 | High-speed differential logic multiplexer A circuit for a high speed digital multiplexer has an active load circuit connected to an output of the digital multiplexer. The active load circuit loads the multiplexer output with a transimpedance stage with low input resistance to reduce the RC time constant at ... | 04/03/2007 |
| 7181966 | Physical quantity sensor and method for manufacturing the same A capacitance type humidity sensor includes: a detection substrate including a detection portion on a first side of the detection substrate; and a circuit board including a circuit portion. The detection portion detects humidity on the basis of capacitance change of... | 02/27/2007 |
| 7176725 | Fast pulse powered NOR decode apparatus for semiconductor devices A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and th... | 02/13/2007 |
| 7173858 | Nonvolatile memory and method of driving the same The nonvolatile memory according to the present invention can precisely read information included in a memory transistor subject to a shift phenomenon because electrical read is performed on the memory transistor by using a reference voltage generated from a refresh... | 02/06/2007 |
| 7170320 | Fast pulse powered NOR decode apparatus with pulse stretching and redundancy steering A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and th... | 01/30/2007 |