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| Number | Title | Issue Date |
| 7439128 | Method of creating deep trench capacitor using a P+ metal electrode The present invention comprises a method including the steps of providing a substrate; forming a trench in the substrate; forming a buried plate in the substrate about the trench; depositing a dielectric layer within the trench; and then depositing a P-type metal at... | 10/21/2008 |
| 7420238 | Semiconductor constructions The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conduc... | 09/02/2008 |
| 7405122 | Methods for fabricating a capacitor A method for forming a capacitor comprises providing a substrate. A bottom electrode material layer is formed on the substrate. A first mask layer is formed on the bottom electrode material layer. A second mask layer is formed on the first mask layer. The second mas... | 07/29/2008 |
| 7402889 | Semiconductor device and method for manufacturing the same Disclosed is a metal-insulator-metal (MIM) capacitor structure formed by a metal interconnection process of trench-exposed metal layers formed on stacked interlayer insulating layers. The MIM capacitor uses a conductive layer conformally formed on the metal intercon... | 07/22/2008 |
| 7402860 | Method for fabricating a capacitor The present invention relates to a method of fabricating a capacitor in a semiconductor substrate. The capacitor is fabricated such that the capacitor comprises: a trench inside a substrate, the trench having a lower region and an upper region, wherein the trench's ... | 07/22/2008 |
| 7384842 | Methods involving silicon-on-insulator trench memory with implanted plate A method for fabricating silicon-on-insulator (SOI) trench memory includes forming a trench on a substrate, wherein a buried oxide layer is disposed on the substrate, a SOI layer is disposed on the buried oxide layer, and a hardmask layer is disposed on the SOI laye... | 06/10/2008 |
| 7344953 | Process for vertically patterning substrates in semiconductor process technology by means of inconformal deposition On a substrate surface, which has been patterned in the form of a relief, of a substrate, typically of a semiconductor wafer, a deposition process is used to provide a covering layer on process surfaces which are vertical or inclined with respect to the substrate su... | 03/18/2008 |
| 7335553 | Method for forming trench capacitor and memory cell A method for forming a trench capacitor and memory cell by providing a substrate on which a grid STI and a plurality of active regions covered by a hard mask layer are formed. A photoresist is formed and a low grade photo mask having only X direction consideration i... | 02/26/2008 |
| 7332392 | Trench-capacitor DRAM device and manufacture method thereof A trench capacitor structure includes a semiconductor substrate comprising thereon a STI structure. A capacitor deep trench is etched into the semiconductor substrate. Collar oxide layer is disposed on inner surface of the capacitor deep trench. A first doped polysi... | 02/19/2008 |
| 7326986 | Trench memory A trench device and method for fabricating same are provided. The trench device has a collar with a first portion that is doped and a second portion that is undoped. Fabrication of the partially doped collar can be done by deposition of a doped insulator in the tren... | 02/05/2008 |
| 7326612 | Method for fabricating a semiconductor structure A method is provided for fabricating a semiconductor structure, such as a DRAM memory cell, that includes an elevated region with at least one sidewall. The at least one sidewall is provided with an insulation layer. A mask layer is applied to the insulation layer. ... | 02/05/2008 |
| 7320912 | Trench capacitors with buried isolation layer formed by an oxidation process and methods for manufacturing the same A method for forming a trench capacitor includes: removing a portion of the substrate to form a trench within the substrate; forming at a buried isolation layer within the substrate; forming in the substrate a first electrode of the trench capacitor at least in area... | 01/22/2008 |
| 7315054 | Decoupling capacitor density while maintaining control over ACLV regions on a semiconductor integrated circuit In one embodiment, a method of controlling the across-chip line-width variation (ACLV) on a semiconductor integrated circuit includes forming an ACLV controlled region including a plurality of semiconductor devices each having a gate structure and arranging the plur... | 01/01/2008 |
| 7312115 | Fabrication method for a semiconductor structure having integrated capacitors The present invention provides a fabrication method for a semiconductor structure having integrated capacitors and a corresponding semiconductor structure. The fabrication method has the following steps of: providing a semiconductor substrate (1; 1′, 60, 1â... | 12/25/2007 |
| 7262452 | Method of forming DRAM device having capacitor and DRAM device so formed In a method of forming a DRAM device having a capacitor and a DRAM device so formed, an interlayer dielectric having at least one layer is formed on a semiconductor substrate. The interlayer dielectric layer and a predetermined portion of the semiconductor substrate... | 08/28/2007 |
| 7256439 | Trench capacitor array having well contacting merged plate According to an aspect of the invention, a structure is provided in which an array of trench capacitors includes a well contact to a merged buried plate diffusion region. The array, which is disposed in a substrate, includes a contact for receiving a reference poten... | 08/14/2007 |
| 7250336 | Method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure The present invention provides a method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure, comprising the steps of: providing a trench in the microelectronic or micromechanical structure; providing a partial filling in the t... | 07/31/2007 |
| 7235453 | Method of fabricating MIM capacitor A method of fabricating an MIM capacitor is provided, by which higher capacitance can be secured per unit volume or area by forming a dual-stack type capacitor to increase an effective area of the capacitor. The method includes patterning a first metal layer, formin... | 06/26/2007 |
| 7232718 | Method for forming a deep trench capacitor buried plate A method for forming a deep trench capacitor buried plate. A substrate having a pad oxide and a pad nitride is provided. A deep trench is formed in the substrate. A doped silicate film is deposited on a sidewall of the deep trench. A sacrificial layer is deposited i... | 06/19/2007 |
| 7232719 | Memories having a charge storage node at least partially located in a trench in a semiconductor substrate and electrically coupled to a source/drain region formed in the substrate A memory charge storage node (120.1, 120.2, 120.3) is at least partially located in a trench (124). The memory comprises a transistor including a source/drain region (170) present at a first side (124.1) but not a second side (124.2 | 06/19/2007 |
| 7214982 | Semiconductor memory device and method of manufacturing the same A semiconductor device including a ferroelectric random access memory, which has a structure suitable for miniaturization and easy to manufacture, and having less restrictions on materials to be used, comprises a field effect transistor formed on a surface area of a... | 05/08/2007 |
| 7211483 | Memory device with vertical transistors and deep trench capacitors and method of fabricating the same A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a... | 05/01/2007 |
| 7208789 | DRAM cell structure with buried surrounding capacitor and process for manufacturing the same A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and... | 04/24/2007 |
| 7164188 | Buried conductor patterns formed by surface transformation of empty spaces in solid state materials A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns are formed by drilling holes in the monocrystalline substrate and annealing the monocrystalline substrat... | 01/16/2007 |
| 7071054 | Methods of fabricating MIM capacitors in semiconductor devices Methods of fabricating an MIM capacitor and a dual damascene structure of a semiconductor device are disclosed. According to one example, a method includes depositing a first insulating layer on a semiconductor substrate; forming a lower interconnect through the fir... | 07/04/2006 |
| 7009238 | Deep-trench capacitor with hemispherical grain silicon surface and method for making the same A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrif... | 03/07/2006 |
| 6703273 | Aggressive capacitor array cell layout for narrow diameter DRAM trench capacitor structures via SOI technology A method of increasing DRAM cell capacitance via formation of deep, wide diameter trench capacitor structures, has been developed. An underlying semiconductor substrate is used to accommodate deep, wide diameter trench capacitor structures while an overly... | 03/09/2004 |
| 6699794 | Self aligned buried plate A method of forming a buried plate in a silicon substrate uses a silicon substrate having a deep trench etched into the silicon substrate. A highly doped polysilicon layer is formed within the trench. A nitride layer is then formed within the trench over ... | 03/02/2004 |
| 6693006 | Method for increasing area of a trench capacitor A method for increasing area of a trench capacitor. First, a first oxide layer and a first nitride layer are sequentially formed on a substrate. An opening is formed through the first oxide layer and the first nitride layer into the substrate. A part of t... | 02/17/2004 |
| 6667504 | Self-aligned buried strap process using doped HDP oxide The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capaci... | 12/23/2003 |
| 6664161 | Method and structure for salicide trench capacitor plate electrode The present invention is a method and structure for fabricating a trench capacitor within a semiconductor substrate having a buried plate electrode formed of metal silicide. A collar is formed in a trench etched into a substrate; a conformal metal film is... | 12/16/2003 |
| 6661049 | Microelectronic capacitor structure embedded within microelectronic isolation region Within a method for fabricating a capacitor structure, and a capacitor structure fabricated employing the method, there is formed within an isolation region adjoining an active region of a semiconductor substrate a laterally asymmetric trench which leaves... | 12/09/2003 |
| 6649959 | Method for increasing a very-large-scale-integrated (VLSI) capacitor size on bulk silicon and silicon-on-insulator (SOI) wafers and structure formed thereby A method of forming a semiconductor device, includes forming at least one conductive island having a predetermined sidewall angle in a conductive substrate, forming a dielectric material over the at least one island, forming a conductive material over the... | 11/18/2003 |
| 6635915 | Semiconductor device having trench capacitor formed in SOI substrate A semiconductor device comprises an SOI substrate, a trench, a trench capacitor, and a conductive layer. The SOI substrate includes a fist semiconductor region, a buried insulating film formed on the first semiconductor region, and a second semiconductor ... | 10/21/2003 |
| 6635526 | Structure and method for dual work function logic devices in vertical DRAM process Dual work function transistors are provided in a cmos support area 14 with an embedded vertical dram array 12. A wordline layer 54, and nitride cap layer 56 cover the dram array 12 and a gate oxide layer 42 and an undoped polysilicon layer 44 cover the su... | 10/21/2003 |
| 6620675 | Increased capacitance trench capacitor Disclosed is a method of increasing the capacitance of a trench capacitor by increasing sidewall area, comprising: forming a trench in a silicon substrate, the trench having a sidewall; forming islands on the sidewall of the trench; and etching pits into ... | 09/16/2003 |
| 6610567 | DRAM having a guard ring and process of fabricating the same A DRAM having a guard ring comprises a semiconductor substrate having a memory array area and a guard ring area; a first trench disposed on said memory array area; a second trench disposed on said guard ring area; a first doped strap disposed on the upper... | 08/26/2003 |
| 6605838 | Process flow for thick isolation collar with reduced length A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The verti... | 08/12/2003 |
| 6599798 | Method of preparing buried LOCOS collar in trench DRAMS The vertical DRAM capacitor with a buried LOCOS collar characterized by: a self-aligned bottle and gas phase doping; no consumption of silicon at the depth of the buried strap; no reduction of trench diameter; and a nitride layer to protect trench sidewal... | 07/29/2003 |
| 6566191 | Forming electronic structures having dual dielectric thicknesses and the structure so formed A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.... | 05/20/2003 |
