...that Robert Adler has the dubious distinction of being the Father of the Couch Potato? Back in 1955 Adler was employed by what was then Zenith Radio Corp., where he was charged to invent something that would allow viewers to turn down the TV volume without leaving their chairs. After a series of flops (such as a wired contraption that people tripped over), Adler hit on the idea of using sound waves. Thus the Remote Control was born...
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| Number | Title | Issue Date |
| 6700157 | Semiconductor device A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions an... | 03/02/2004 |
| 6627948 | Vertical layer type semiconductor device A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions an... | 09/30/2003 |
| 6545340 | Semiconductor device A semiconductor device of the invention in the form of a superlattice-heterojunction bipolar transistor (SL-HBT) 10 incorporates a superlattice region 16 within an emitter mesa 21. The superlattice region 16 provides a non-linear response to a sufficientl... | 04/08/2003 |
| 6503782 | Complementary accumulation-mode JFET integrated circuit topology using wide (>2eV) bandgap semiconductors A method and device produced for design, construction, and use of integrated circuits in wide bandgap semiconductors, including methods for fabrication of n-channel and p-channel junction field effect transistors on a single wafer or die, such that the pr... | 01/07/2003 |
| 6486520 | Structure and method for a large-permittivity gate using a germanium layer A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a... | 11/26/2002 |
| 6486011 | JFET structure and manufacture method for low on-resistance and low voltage application This invention discloses the present invention discloses a junction field effect transistor (JFET) device supported on a substrate. The JFET device includes a gate surrounded by a depletion region. As the distance between the gates is large enough, there ... | 11/26/2002 |
| 6468890 | Semiconductor device with ohmic contact-connection and method for the ohmic contact-connection of a semiconductor device The disclosed semiconductor device comprises an ohmic contact between a semiconductor region made of n-conducting silicon carbide and a largely homogeneous ohmic contact layer (110), which adjoins the semiconductor region and is made of a material having ... | 10/22/2002 |
| 6365919 | Silicon carbide junction field effect transistor A lateral silicon carbide junction field effect transistor has p-conductive and n-conductive silicon carbide layers. The layers are provided in pairs in lateral direction in a silicon carbide body. Trenches for a source, a drain and a gate extend from a p... | 04/02/2002 |
| 6344116 | Monocrystalline three-dimensional integrated-circuit technology Three technologies realize monocrystalline three-dimensional (3-D) integrated circuits: (1) silicon sputter epitaxy permitting fast growth at low temperature; (2) real-time pattern generation using a pixel-by-pixel programmable device to create a patterne... | 02/05/2002 |
| 6307223 | Complementary junction field effect transistors Junction Field Effect Transistor (JFET) offers fast switching speed than bipolar transistor since JFET is a majority carrier device. This invention comprises two normally "off" JFETs, one in N-channel and one in P-channel to form Complementary Junction Fi... | 10/23/2001 |
| 6287903 | Structure and method for a large-permittivity dielectric using a germanium layer A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a... | 09/11/2001 |
| 6285046 | Controllable semiconductor structure with improved switching properties The invention concerns a controllable semiconductor structure comprising a base region (101, 201, 301, 401), a source region (106, 212, 312, 412) and a drain region (107, 213, 313, 413) a conductive duct being provided in the base region between the sourc... | 09/04/2001 |
| 6271550 | Junction field effect transistor or JFET with a well which has graded doping directly beneath the gate electrode In a channel well of a semiconductive substrate, source, drain and gate electrodes are formed. Below the gate electrode region, a plurality of partial regions of the second conductive type are arranged next to each other in the direction of the extension ... | 08/07/2001 |
| 6251716 | JFET structure and manufacture method for low on-resistance and low voltage application This invention discloses the present invention discloses a junction field effect transistor UFET) device supported on a substrate. The JFET device includes a gate surrounded by a depletion region. As the distance between the gates is large enough, there i... | 06/26/2001 |
| 6201269 | Junction field effect transistor and method of producing the same For suppressing generation of leakage current and side-gate effect in a junction field effect transistor, a gate extension is formed on a semi-insulative compound semiconductor substrate in a manner to extend from a gate and to protrude outward beyond a c... | 03/13/2001 |
| 6051856 | Voltage-controlled resistor utilizing bootstrap gate FET An improved FET for use as a voltage-controlled resistor includes a p-type control gate and a high-resistance connection to receive a control signal. The bootstrap frequency for the device is much lower than the signal frequency so that the signal frequen... | 04/18/2000 |
| 6020607 | Semiconductor device having junction field effect transistors An N- type epitaxial layer is formed on a P type semiconductor substrate, and a P+ type insulative isolating layer is so formed as to reach the semiconductor substrate from the surface of the N- type epitaxial layer to ... | 02/01/2000 |
| 6020608 | Junction-type field-effect transistor with improved impact-ionization resistance Junction-type field-effect transistors are disclosed exhibiting improved resistance to impact ionization. A p-type gate region is formed above an n-type channel region between an n-type drain region and an n-type source region each having a high impurity ... | 02/01/2000 |
| 6005266 | Very low leakage JFET for monolithically integrated arrays A low leakage current monolithic InGaAs InP discrete device is provided for a focal plane array for near-infrared imaging. The array consists of a plurality of InGaAs p-i-n diodes for photodetectors, with each being integrated on a common substrate with a... | 12/21/1999 |
| 5937318 | Monocrystalline three-dimensional integrated circuit A monocrystalline monolith contains a 3-D array of interconnected lattice-matched devices (which may be of one kind exclusively, or that kind in combination with one or more other kinds) performing digital, analog, image-processing, or neural-network func... | 08/10/1999 |
| 5907168 | Low noise Ge-JFETs A Germanium junction field effect transistor (Ge-JFET) is fabricated in a manner to produce low noise and which is particularly suitable for a cryogenic detector. The Ge-JFET in accordance with the present invention comprises a germanium base material on ... | 05/25/1999 |
| 5866925 | Gallium nitride junction field-effect transistor An all-ion implanted gallium-nitride (GaN) junction field-effect transistor (JFET) and method of making the same. Also disclosed are various ion implants, both n- and p-type, together with or without phosphorous co-implantation, in selected III-V semicond... | 02/02/1999 |
| 5824575 | Semiconductor device and method of manufacturing the same After forming an n-type active layer, an n+ -type source region and an n+ -type drain region at predetermined regions of a GaAs substrate, a silicon oxide film and a silicon nitride film are deposited, and then source and drain elect... | 10/20/1998 |
| 5807780 | High frequency analog transistors method of fabrication and circuit implementation A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, l... | 09/15/1998 |
| 5726469 | Surface voltage sustaining structure for semiconductor devices A surface voltage sustaining structure around an n+ (or p+)-type region on a p- (or n-)-type substrate for high-voltage devices is made by a combination of n-type regions and/or p-type regions and produces an ... | 03/10/1998 |
| 5668397 | High frequency analog transistors, method of fabrication and circuit implementation A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, l... | 09/16/1997 |
| 5641695 | Method of forming a silicon carbide JFET An implant mask (14) and an etch mask (16) are utilized in forming a silicon carbide JFET (10). A source opening (17) and a drain opening (18) are formed in the masks (14,16). The etch mask (16) is removed, and a source area (19) and a drain area 21 are i... | 06/24/1997 |
| 5639688 | Method of making integrated circuit structure with narrow line widths In a sub-micron line width process, a first layer of polysilicon 13 is patterned into lines 1,2 spaced a predetermined distance. An oxide layer 11 is deposited. A second layer of polysilicon 14 is deposited on the insulating layer. A gate contact 19 or em... | 06/17/1997 |
| 5627389 | High-frequency traveling wave field-effect transistor A method of improving the performance of a traveling wave field-effect transistor operated at frequencies in the microwave range or above the microwave range comprising the steps of forming a depletion region beneath a gate electrode wherein, in a plane t... | 05/06/1997 |
| 5559346 | Field-effect semiconductor device with increased breakdown voltage A field-effect semiconductor device for reducing on-state source-drain voltage and increasing breakdown voltage, has a one conductivity type semiconductor region, a source region of one conductivity type, a drain region, and gate regions of other conducti... | 09/24/1996 |
| 5510632 | Silicon carbide junction field effect transistor device for high temperature applications A silicon carbide (SiC) junction field effect transistor (JFET) device is fabricated upon a substrate layer, such as a p type conductivity SiC substrate, using ion implantation for the source and drain areas. A SiC p type conductivity layer is epitaxially... | 04/23/1996 |
| 5459343 | Back gate FET microwave switch A semiconductor device which includes a channel region of predetermined conductivity type having a pair of opposing surfaces (11 or 33) , a control element of opposite conductivity type disposed on one of the opposing surfaces (13 or 31) and a pair of spa... | 10/17/1995 |
| 5428232 | Field effect transistor apparatus A dual gate field effect transistor including first and second gates comprises a conductive region, wherein a potential difference between a second gate electrode section and the conductive region is larger than that between the second gate electrode sect... | 06/27/1995 |
| 5382809 | Semiconductor device including semiconductor diamond A semiconductor device having an MISFET-like structure. The semiconductor device comprises: an p-type semiconductor diamond layer disposed on an insulating diamond substrate for providing a channel region; and a drain electrode, a source electrode and a g... | 01/17/1995 |
| 5378642 | Method of making a silicon carbide junction field effect transistor device for high temperature applications A silicon carbide (SiC) junction field effect transistor (JFET) device is fabricated upon a substrate layer, such as a p type conductivity SiC substrate, using ion implantation for the source and drain areas. A SiC p type conductivity layer is epitaxially... | 01/03/1995 |
| 5359214 | Field effect devices formed from porous semiconductor materials A field effect transistor device constructed in accordance with the present invention includes a channel of semiconductive material such as silicon having at least one row of pores extending therethrough. Internal pn junctions are fabricated within the po... | 10/25/1994 |
| 5338949 | Semiconductor device having series-connected junction field effect transistors A JFET configuration is obtained whose pinch-off voltage can be set by means of mask dimensions, without process changes, and which is at the same time suitable for operation at very low and very high voltages by cascoding of a first JFET with a diffused ... | 08/16/1994 |
| 5319227 | Low-leakage JFET having increased top gate doping concentration A low-leakage-current JFET having electrically isolated top and bottom gates. The structure employs enclosed geometry wherein one source/drain region fully surrounds the other source/drain region. Connection to the top gate is made through a diffusion-bar... | 06/07/1994 |
| 5309007 | Junction field effect transistor with lateral gate voltage swing (GVS-JFET) A field effect transistor having a buried gate, and one or more gates disposed along the channel between the source and drain, which cooperate to cause the electric field within the channel along its length to be more uniform, and have a lower field maxim... | 05/03/1994 |
| 5309006 | FET crossbar switch device particularly useful for microwave applications An FET crossbar switch device is implemented by using a split gate electrode and a shared source and drain pad to implement source and drain electrodes on an integrated circuit substrate. First and second inputs to the device are associated with first and... | 05/03/1994 |