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A method of swing on a swing is disclosed, in which a user positioned on a standard swing suspended by two chains from a substantially horizontal tree branch induces side to side motion by pulling alternately on one chain and then the other.
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| Number | Title | Issue Date |
| 7439577 | Semiconductor memory and method for manufacturing the same A semiconductor memory is provided with memory cells including bit lines made of a diffusion layer formed in a semiconductor substrate, charge-trapping gate insulating films formed between the bit lines and word lines formed on the gate insulating films. An interlay... | 10/21/2008 |
| 7413950 | Methods of forming capacitors having storage electrodes including cylindrical conductive patterns A capacitor is provided including a storage node contact pad and a storage electrode. The storage electrode includes at least two cylindrical conductive patterns. The at least two cylindrical conductive patterns are electrically coupled to a portion of a surface of ... | 08/19/2008 |
| 7411247 | Twin insulator charge storage device operation and its fabrication method The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the pro... | 08/12/2008 |
| 7410857 | Semiconductor memory device and manufacturing method thereof After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is form... | 08/12/2008 |
| 7402868 | System and method for protecting semiconductor devices A semiconductor memory device includes a group of word lines and a structure that is configured to dissipate current from the group of word lines during fabrication of the semiconductor memory device. ... | 07/22/2008 |
| 7400012 | Scalable Flash/NV structures and devices with extended endurance Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel medium, a high K charge blocking and charge storing medium, and an inject... | 07/15/2008 |
| 7394128 | Semiconductor memory device with channel regions along sidewalls of fins A semiconductor memory (26) having a plurality of memory cells (25), the semiconductor memory (26) having a substrate (1), at least one wordline (2) and first (3) and second lines (4). Each memory cell (25) of ... | 07/01/2008 |
| 7391078 | Non-volatile memory and manufacturing and operating method thereof A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjace... | 06/24/2008 |
| 7388245 | Semiconductor device, method for manufacturing the semiconductor device and portable electronic device provided with the semiconductor device A semiconductor device, which is characterized by that two or more island-shaped semiconductor layers including first and second island-shaped semiconductor layers are formed on the same substrate, at least the first island-shaped semiconductor layer has steps in it... | 06/17/2008 |
| 7385245 | Low power memory subsystem with progressive non-volatility The memory system is comprised of a plurality of memory arrays that are coupled to a processor. The memory arrays are comprised of non-volatile memory cells that have read/write speeds and charge retention times that are different from the other memory arrays of the... | 06/10/2008 |
| 7365389 | Memory cell having enhanced high-K dielectric A semiconductor memory device may include an intergate dielectric layer of a high-K, high barrier height dielectric material interposed between a charge storage layer and a control gate. With this intergate high-K, high barrier height dielectric in place, the memory... | 04/29/2008 |
| 7355236 | Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof. The non-volatile floating gate memory cell comprises a semiconductor substrate of a first conductivity type. A first region of a second conductivity type different... | 04/08/2008 |
| 7352024 | Semiconductor storage device and semiconductor integrated circuit There is provided a semiconductor storage device capable of high integration. On a top surface of a semiconductor substrate, a plurality of device isolation regions (16) each extending and meandering in a lateral direction are formed so as to be arrayed with ... | 04/01/2008 |
| 7345336 | Semiconductor memory device having self-aligned charge trapping layer A semiconductor memory device having a self-aligned charge trapping layer and a method of manufacturing the same in which a consistent length of an ONO layer is ensured. Here, an insulating stacked structure is self-aligned to a bottom surface of conductive spacers.... | 03/18/2008 |
| 7342277 | Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric materia... | 03/11/2008 |
| 7342279 | Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than tw... | 03/11/2008 |
| 7332768 | Non-volatile memory devices Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, program... | 02/19/2008 |
| 7332789 | Isolation trenches for memory devices Methods and apparatus are provided. A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first diele... | 02/19/2008 |
| 7317222 | Memory cell using a dielectric having non-uniform thickness A memory cell is programmed by injecting charge into a charge storage layer of the memory cell. A desired programmed charge results in the charge storage layer over an edge portion of a channel region of the memory cell. An undesired programmed charge results in the... | 01/08/2008 |
| 7315059 | Semiconductor memory device and manufacturing method for the same The present invention provides a semiconductor memory device having one or more protruding semiconductor layers formed on a semiconductor substrate of a first conductivity type and a plurality of memory cells on surfaces of the protruding semiconductor layers, where... | 01/01/2008 |
| 7315060 | Semiconductor storage device, manufacturing method therefor and portable electronic equipment A semiconductor storage device has a single gate electrode formed on a semiconductor substrate through a gate insulation film. First and second memory function bodies formed on both sides of the gate electrode. A P-type channel region is formed in a surface of the s... | 01/01/2008 |
| 7312499 | Semiconductor storage device and manufacturing method therefor, semiconductor device, portable electronic equipment and IC card A semiconductor storage device includes a field effect transistor which has a gate insulator, a gate electrode and a pair of source/drain diffusion regions on a semiconductor substrate. The device also includes a coating film made of a dielectric having a function o... | 12/25/2007 |
| 7307296 | Flash memory and fabrication method thereof A flash memory comprises a substrate, control gates, doped regions, an isolation layer, isolation structures, floating gates, tunneling dielectric layers and inter-gate dielectric layers. The control gates are arranged over the substrate with a first direction, and ... | 12/11/2007 |
| 7307280 | Memory devices with active and passive doped sol-gel layers The present memory device includes first and second electrodes, an active layer; and a passive layer, the active and passive layers being between the first and second electrodes, with at least one of the active layer and passive layer being a doped a sol-gel. ... | 12/11/2007 |
| 7306991 | Stepped gate configuration for non-volatile memory A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor substrate and consists of a pair of charge trapping dielectrics separated b... | 12/11/2007 |
| 7304346 | Flash memory cell transistor and method for fabricating the same A flash memory cell transistor and a method for fabricating the same compensates a work function difference of a pMOS and a nMOS with a triple gate insulating film by using electron density trapped in a pMOS gate insulating film. The flash memory cell transistor com... | 12/04/2007 |
| 7301198 | Semiconductor device having logic circuitry and memory circuitry on the same substrate, and its use in portable electronic equipment and IC card A semiconductor switching element and a semiconductor storage element each have a gate electrode, a pair of source/drain regions and a channel forming region. Memory function bodies having a function of storing electric charges are provided on opposite sides of the ... | 11/27/2007 |
| 7268389 | Nonvolatile semiconductor memory A nonvolatile semiconductor memory device includes diffusion layers formed in a semiconductor substrate, a gate insulating film formed on at least a portion of a channel region between the diffusion layers in the semiconductor substrate, and a control gate formed on... | 09/11/2007 |
| 7265414 | NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant greater than silicon dioxide and is comprised of a nanolaminate structure. The NROM memory cell has a substrat... | 09/04/2007 |
| 7265413 | Semiconductor memory with vertical memory transistors and method for fabricating it The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory generally includes a semiconductor layer arranged on a substrate surface that includes a normally positioned ste... | 09/04/2007 |
| 7265016 | Stepped gate configuration for non-volatile memory A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor substrate and consists of a pair of charge trapping dielectrics separated b... | 09/04/2007 |
| 7265410 | Non-volatile memory cell having a silicon-oxide-nitride-oxide-silicon gate structure and fabrication method of such cell A non-volatile memory cell able to be written in a first direction and read in a second direction is described. The memory cell includes one or two charge trapping regions located near either the source or the drain, or both the source and the drain. During a progra... | 09/04/2007 |
| 7259423 | Non-volatile memory device having dual gate A non-volatile memory device including a control gate pattern having a tunnel insulation pattern, a trap-insulation pattern, a blocking insulation pattern and a control gate electrode, which are stacked on a semiconductor substrate. A selection gate pattern is dispo... | 08/21/2007 |
| 7256451 | NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant greater than silicon dioxide and is comprised of a nanolaminate structure. The NROM memory cell has a substrat... | 08/14/2007 |
| 7256450 | NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant greater than silicon dioxide and is comprised of a nanolaminate structure. The NROM memory cell has a substrat... | 08/14/2007 |
| 7256452 | NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant greater than silicon dioxide and is comprised of a nanolaminate structure. The NROM memory cell has a substrat... | 08/14/2007 |
| 7244986 | Two-bit cell semiconductor memory device A 2-bit cell is made up of first and second diffusion regions provided on a substrate surface, first and second storage nodes adjacent to the first and second diffusion region, first and second gate electrodes provided on first and second storage nodes, a third stor... | 07/17/2007 |
| 7238984 | Semiconductor memory device, semiconductor device, and portable electronic apparatus A semiconductor memory device includes a nonvolatile memory section; and a volatile memory section, wherein the nonvolatile memory section includes a nonvolatile memory cell having a gate electrode formed on a semiconductor layer via a gate insulating film, a channe... | 07/03/2007 |
| 7227220 | Semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity typ... | 06/05/2007 |
| 7221018 | NROM flash memory with a high-permittivity gate dielectric A high permittivity gate dielectric is used in an NROM memory cell. The gate dielectric has a dielectric constant greater than silicon dioxide and is comprised of an atomic layer deposited and/or evaporated nanolaminate structure. The NROM memory cell has a substrat... | 05/22/2007 |
