Did You Know...
...During the Civil War, the Confederacy established its own Patent Office which issued 266 patents, a third of which concerned implements of war.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7442986 | Nonvolatile semiconductor memory device with tapered sidewall gate and method of manufacturing the same In a split gate type nonvolatile memory cell in which a MOS transistor for a nonvolatile memory using a charge storing film and a MOS transistor for selecting it are adjacently formed, the charge storing characteristic is improved and the resistance of the gate elec... | 10/28/2008 |
| 7442987 | Non-volatile memory devices including divided charge storage structures A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel ... | 10/28/2008 |
| 7439571 | Method for fabricating metal gate structures Methods of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer, and then laser annealing the sub... | 10/21/2008 |
| 7429765 | Nonvolatile semiconductor memory A nonvolatile semiconductor memory includes: a device region and a device isolating region, which have a pattern with a striped form that extends in a first direction, and are alternately and sequentially disposed at a first pitch in a second direction that is perpe... | 09/30/2008 |
| 7425741 | EEPROM structure with improved data retention utilizing biased metal plate and conductive layer exclusion A biased conductive plate is provided over an NVM cell structure to overcome data retention charge loss due to the presence of dielectric films that are conductive at higher temperatures. The biased conductive plate is preferably formed from the lowest metal layer i... | 09/16/2008 |
| 7417278 | Method to increase coupling ratio of source to floating gate in split-gate flash A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with... | 08/26/2008 |
| 7411243 | Nonvolatile semiconductor device and method of fabricating the same A nonvolatile semiconductor device and a method of fabricating the same are provided. The nonvolatile semiconductor device includes a semiconductor body formed on a substrate to be elongated in one direction and having a cross section perpendicular to a main surface... | 08/12/2008 |
| 7411246 | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby A method of forming an array of floating gate memory cells, and an array formed thereby, that includes source and drain regions formed in a substrate, and a conductive block of material disposed over the source region. The floating gate is formed as a thin, L-shaped... | 08/12/2008 |
| 7405440 | Nonvolatile semiconductor memory A nonvolatile semiconductor memory on a semiconductor chip includes: a cell array region configured with a memory cell transistor having a first metallic salicide film, a first control gate electrode electrically coupled with the first metallic salicide film, and a ... | 07/29/2008 |
| 7400010 | Semiconductor device and method of manufacturing the same A semiconductor device including a semiconductor substrate having trenches oriented in a predetermined direction; a gate insulating film overlaying the semiconductor substrate interposed between the trenches; and floating gate electrodes formed on the gate insulatin... | 07/15/2008 |
| 7397079 | Non-volatile memory device and methods of forming the same A non-volatile memory device includes a control gate electrode disposed on a substrate with a first insulation layer interposed therebetween and a floating gate disposed in a hole exposing substrate through the control gate electrode and the first insulation layer. ... | 07/08/2008 |
| 7391075 | Non-volatile semiconductor memory device with alternative metal gate material A non-volatile semiconductor memory device comprises a substrate including a source region, a drain region and a channel region provided between the source region and the drain region with a gate stack located above the channel region with a metal gate located above... | 06/24/2008 |
| 7391074 | Nanowire based non-volatile floating-gate memory A non-volatile memory transistor with a nanocrystal-containing floating gate formed by nanowires is disclosed. The nanocrystals are formed by the growth of short nanowires over a crystalline program oxide. As a result, the nanocrystals are single-crystals of uniform... | 06/24/2008 |
| 7391078 | Non-volatile memory and manufacturing and operating method thereof A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjace... | 06/24/2008 |
| 7387933 | EEPROM device and method of fabricating the same A memory device comprises a semiconductor substrate of a first conductive type, a memory transistor, a select transistor, a floating junction region, a common source region, and a bit line junction region. The floating junction region is formed of a second conductiv... | 06/17/2008 |
| 7385243 | Floating gate memory cell with a metallic source/drain and gate, and method for manufacturing such a floating gate memory gate cell Floating gate memory cell having a first layer with first and second source/drain regions and a channel region arranged between and next to the first and second source/drain regions, and a floating gate layer arranged on the first layer, wherein the first and second... | 06/10/2008 |
| 7375393 | Non-volatile memory (NVM) retention improvement utilizing protective electrical shield An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created ... | 05/20/2008 |
| 7372098 | Low power flash memory devices A buried bipolar junction is provided in a floating gate transistor flash memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and ... | 05/13/2008 |
| 7368780 | Semiconductor memory device and method of manufacturing the same A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each... | 05/06/2008 |
| 7361554 | Multi-bit non-volatile memory device, method of operating the same, and method of manufacturing the multi-bit non-volatile memory device Disclosed are a multi-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the multi-bit non-volatile memory device may be formed on a semiconductor substrate may inclu... | 04/22/2008 |
| 7361951 | Flash memory having memory section and peripheral circuit section A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the eleme... | 04/22/2008 |
| 7355241 | Non-volatile memory A non-volatile memory including a substrate, a select gate, two floating gates, a control gate, and a doped region is described. The select gate is disposed on the substrate. The two floating gates are disposed on both sides of the select gate, and the top surface o... | 04/08/2008 |
| 7355240 | Semiconductor product including logic, non-volatile memory and volatile memory devices and method for fabrication thereof A semiconductor product and a method for fabricating the semiconductor product employ a semiconductor substrate. The semiconductor substrate has a logic region having a logic device formed therein, a non-volatile memory region having a non-volatile memory device for... | 04/08/2008 |
| 7352024 | Semiconductor storage device and semiconductor integrated circuit There is provided a semiconductor storage device capable of high integration. On a top surface of a semiconductor substrate, a plurality of device isolation regions (16) each extending and meandering in a lateral direction are formed so as to be arrayed with ... | 04/01/2008 |
| 7338866 | Strapping word lines of NAND memory devices Conductive straps are connected to a subset of word lines of a memory device. Alternatively, first conductive straps are respectively connected only to first portions of first word lines of a memory device, and second conductive straps are respectively connected onl... | 03/04/2008 |
| 7335937 | Nonvolatile semiconductor memory In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1... | 02/26/2008 |
| 7315073 | Semiconductor device having an oxide film formed on a semiconductor substrate sidewall of an element region and on a sidewall of a gate electrode A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A se... | 01/01/2008 |
| 7315056 | Semiconductor memory array of floating gate memory cells with program/erase and select gates A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an el... | 01/01/2008 |
| 7309892 | Semiconductor element and semiconductor memory device using the same A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so ... | 12/18/2007 |
| 7309891 | Non-volatile and memory semiconductor integrated circuit A semiconductor integrated circuit device includes first, second gate electrodes, first, second diffusion layers, contact electrodes electrically connected to the first diffusion layers, a first insulating film which has concave portions between the first and second... | 12/18/2007 |
| 7301193 | Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjace... | 11/27/2007 |
| 7298005 | Nonvolatile semiconductor memory and fabrication method for the same A nonvolatile semiconductor memory includes a first and a second active area configured to extend in the column direction in parallel; an element isolating region configured to electrically separate the first and the second active area; a plurality of word lines con... | 11/20/2007 |
| 7282759 | Memory device having serially connected resistance nodes A memory device may include a plurality of resistance nodes. The resistance nodes may be connected serially in a NAND or AND structure, by a plurality of metal plugs. The metal plugs may have a lower resistance. A control device corresponding to each resistance node... | 10/16/2007 |
| 7265411 | Non-volatile memory having multiple gate structure In one embodiment, a semiconductor device comprises an insulated floating gate disposed on a semiconductor substrate, an insulated program gate formed at least on a side surface of the floating gate, and an insulated erase gate disposed adjacent the floating gate. | 09/04/2007 |
| 7259419 | Programmable memory device, integrated circuit including the programmable memory device, and method of fabricating same An integrated circuit comprises a memory device including an isolation layer for defining an active area of a substrate, a tunnel oxide layer formed on the active area, a floating gate formed over the active area and the isolation layer, an inter-gate dielectric lay... | 08/21/2007 |
| 7256448 | Split gate type nonvolatile semiconductor memory device, and method of fabricating the same A split gate type nonvolatile semiconductor memory device and a method of fabricating a split gate type nonvolatile semiconductor memory device are provided. A gate insulating layer and a floating-gate conductive layer are formed on a semiconductor substrate. A mask... | 08/14/2007 |
| 7256447 | Multi-bit non-volatile memory device, method of operating the same, and method of manufacturing the multi-bit non-volatile memory device Disclosed are a muli-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the muli-bit non-volatile memory device may be formed on a semiconductor substrate may include... | 08/14/2007 |
| 7244651 | Fabrication of an OTP-EPROM having reduced leakage current The leakage current of an OTP-EPROM cell formed using buried channel PMOS technology can be reduced. The reduction in leakage current of the OTP-EPROM can be achieved by blocking implantation of the Vtp implant into a channel region of an n-well that subs... | 07/17/2007 |
| 7242049 | Memory device A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the... | 07/10/2007 |
| 7242051 | Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the subst... | 07/10/2007 |
