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| Number | Title | Issue Date |
| 7402505 | Single electron devices formed by laser thermal annealing A semiconductor device with a superlattice and method of making same includes forming a layer of amorphous silicon over a substrate, and forming a layer of nanocrystals by laser thermal annealing the layer of amorphous silicon. A gate dielectric is formed between th... | 07/22/2008 |
| 7394111 | Strained Si/SiGe structures by ion implantation One aspect of this disclosure relates to a method for forming a strained silicon over silicon germanium (Si/SiGe) structure. In various embodiments, germanium ions are implanted into a silicon substrate with a desired dose and energy to be located beneath a surface ... | 07/01/2008 |
| 7381992 | Silicon carbide power devices with self-aligned source and well regions Silicon carbide semiconductor devices and methods of fabricating silicon carbide semiconductor devices are provided by successively etching a mask layer to provide windows for formation of a source region of a first conductivity type, a buried silicon carbide region... | 06/03/2008 |
| 7375368 | Superlattice for fabricating nanowires This disclosure relates to a system and method for creating nanowires. A nanowire can be created by exposing layers of material in a superlattice and dissolving and transferring material from edges of the exposed layers onto a substrate. The nanowire can also be cre... | 05/20/2008 |
| 7332412 | Structure of strained silicon on insulator and method of manufacturing the same Provided is a strained SOI structure and a method of manufacturing the strained SOI structure. The strained SOI structure includes an insulating substrate, a SiO2 layer formed on the insulating substrate, and a strained silicon layer formed on the SiO | 02/19/2008 |
| 7223611 | Fabrication of nanowires This disclosure relates to a system and method for creating nanowires. A nanowire can be created by exposing layers of material in a superlattice and dissolving and transferring material from edges of the exposed layers onto a substrate. The nanowire can also be cre... | 05/29/2007 |
| 7153763 | Method for making a semiconductor device including band-engineered superlattice using intermediate annealing A method for making a semiconductor device may include forming a superlattice including a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at le... | 12/26/2006 |
| 7132298 | Fabrication of nano-object array This disclosure relates to a system and method for creating nano-object arrays. A nano-object array can be created by exposing troughs in a corrugated surface to nano-objects and depositing the nano-objects within or orienting the nano-objects with the troughs. ... | 11/07/2006 |
| 7023010 | Si/C superlattice useful for semiconductor devices A Si/C superlattice useful for semiconductor devices comprises a plurality of epitaxially grown silicon layers alternating with carbon layers respectively adsorbed on surfaces of said silicon layers. Structures and devices comprising the superlattice and methods are... | 04/04/2006 |
| 6690043 | Semiconductor device and method of manufacturing the same A semiconductor device comprises a base substrate, an insulating film formed on the substrate, an undoped first and lattice-relaxed semiconductor layer formed on the insulating film, a second semiconductor layer having a tensile strain and formed on the f... | 02/10/2004 |
| 6635909 | Strained fin FETs structure and method A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side o... | 10/21/2003 |
| 6633066 | CMOS integrated circuit devices and substrates having unstrained silicon active layers CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si | 10/14/2003 |
| 6593191 | Buried channel strained silicon FET using a supply layer created through ion implantation A method of fabricating a buried channel FET including providing a relaxed SiGe layer on a substrate, providing a channel layer on the relaxed SiGe layer, providing a SiGe cap layer on the channel layer, and ion implanting a dopant supply. The dopant supp... | 07/15/2003 |
| 6555839 | Buried channel strained silicon FET using a supply layer created through ion implantation A circuit including at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET. The depletion mode FET includes an ion implanted dopant supply. In exemplary embodiments, the FETs are surface channel or burie... | 04/29/2003 |
| 6512252 | Semiconductor device A HDTMOS includes a Si substrate, a buried oxide film and a semiconductor layer. The semiconductor layer includes an upper Si film, an epitaxially grown Si buffer layer, an epitaxially grown SiGe film, and an epitaxially grown Si film. Furthermore, the HD... | 01/28/2003 |
| 6506654 | Source-side stacking fault body-tie for partially-depleted SOI MOSFET hysteresis control Floating body effects are substantially reduced by strategically forming source-side stacking faults to create a leakage path from the body to the source of an SOI structure. Embodiments include ion implanting a heavy ion, such as Xe, to form a buried amo... | 01/14/2003 |
| 6475869 | Method of forming a double gate transistor having an epitaxial silicon/germanium channel region A method of manufacturing an integrated circuit with a channel region containing germanium. The method can provide a double planar gate structure. The gate structure can be provided over lateral sidewalls of channel region. The semiconductor material cont... | 11/05/2002 |
| 6458662 | Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed A method of fabricating a semiconductor device, having an asymmetrical dual-gate MOSFET with a silicon-germanium (SiGe) channel, involving: patterning a silicon-on-insulator (SOI) wafer with a photoreist layer, wherein the SOI structure comprises a silico... | 10/01/2002 |
| 6410371 | Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer A method of forming a semiconductor-on-insulator (SOI) wafer. The method includes the steps of providing a first wafer, the first wafer having a silicon substrate and an oxide layer disposed thereon; providing a second wafer, the second wafer having a sil... | 06/25/2002 |
| 6403981 | Double gate transistor having a silicon/germanium channel region A method of manufacturing an integrated circuit with a channel region containing germanium. The method includes providing an amorphous semiconductor material including germanium, crystallizing the amorphous semiconductor material, and doping to form a sou... | 06/11/2002 |
| 6365465 | Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal si... | 04/02/2002 |
| 6326667 | Semiconductor devices and methods for producing semiconductor devices The invention is intended to form, on an insulating layer, a thin SiGe layer serving as an underlying layer for obtaining a strained silicon layer, and to provide a satisfactory strained Si layer. A SiGe layer 13 is formed on a Si substrate 11 and an oxyg... | 12/04/2001 |
| 6320202 | Bottom-gated thin film transistors comprising germanium in a channel region A thin film transistor includes, a) a thin film source region; b) a thin film drain region; c) a polycrystalline thin film channel region intermediate the thin film source region and the thin film drain region; d) a transistor gate and gate dielectric ope... | 11/20/2001 |
| 6211531 | Controllable conduction device A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer... | 04/03/2001 |
| 6169308 | Semiconductor memory device and manufacturing method thereof A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhi... | 01/02/2001 |
| 6060723 | Controllable conduction device A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer... | 05/09/2000 |
| 5985703 | Method of making thin film transistors A thin film transistor includes, a) a thin film source region; b) a thin film drain region; c) a polycrystalline thin film channel region intermediate the thin film source region and the thin film drain region; d) a transistor gate and gate dielectric ope... | 11/16/1999 |
| 5985708 | Method of manufacturing vertical power device A semiconductor apparatus comprising a vertical type semiconductor device having a first conducting type semiconductor substrate, a drain layer formed on the surface of the semiconductor substrate, a drain electrode formed on the surface of the drain laye... | 11/16/1999 |
| 5981973 | Thin film transistor structure having increased on-current A thin film transistor structure for use in driving liquid crystal display elements has a semiconductor active layer, a control electrode layer underlying the active layer with an insulating layer interposed therebetween and first and second main electrod... | 11/09/1999 |
| 5977560 | Thin film transistor constructions with polycrystalline silicon-germanium alloy doped with carbon in the channel region A thin film transistor includes, a) a thin film source region; b) a thin film drain region; c) a polycrystalline thin film channel region intermediate the thin film source region and the thin film drain region; d) a transistor gate and gate dielectric ope... | 11/02/1999 |
| 5792679 | Method for forming silicon-germanium/Si/silicon dioxide heterostructure using germanium implant A method for fabricating a GeSi/Si/SiO2 heterostructure comprises the steps of: (a) providing a monocrystalline Si substrate; (b) defining a GeSi region within the Si substrate while leaving a Si cap overlying the GeSi region, the Si cap being ... | 08/11/1998 |
| 5753541 | Method of fabricating polycrystalline silicon-germanium thin film transistor A method for fabricating a silicon-germanium thin film field effect transistor (TFT) with a high carrier mobility and a high on/off ratio. An amorphous silicon layer, an amorphous germanium layer and a gate insulating film are successively layered on an i... | 05/19/1998 |
| 5665981 | Thin film transistors and method of promoting large crystal grain size in the formation of polycrystalline silicon alloy thin films A thin film transistor includes, a) a thin film source region; b) a thin film drain region; c) a polycrystalline thin film channel region intermediate the thin film source region and the thin film drain region; d) a transistor gate and gate dielectric ope... | 09/09/1997 |
| 5493129 | Thin film transistor structure having increased on-current A thin film transistor structure for use in driving liquid crystal display elements has a semiconductor active layer, a control electrode layer underlying the active layer with an insulating layer interposed therebetween and first and second main electrod... | 02/20/1996 |
| 5461250 | SiGe thin film or SOI MOSFET and method for making the same A dual gate thin film or SOI MOSFET device having a sufficiently thin body thickness with one or more semiconductor channel layer(s) sandwiched by semiconductor layers having a different energy band structure to automatically confine carriers to the chann... | 10/24/1995 |
| 5354700 | Method of manufacturing super channel TFT structure An FET thin film transistor is formed with a channel formed of a Si/Si1-x Gex /Si three layer sandwich which serves as the carrier transfer channel. The percentage of germanium is preferably less than 30% and should be less than abou... | 10/11/1994 |
| 5273919 | Method of producing a thin film field effect transistor A method of producing a thin film field effect transistor. An insulating thin film layer is formed on a gate electrode subsequent to the gate electrode being formed on a substrate. A multilayer structure is formed on the insulating thin film layer subsequ... | 12/28/1993 |
| 5221631 | Method of fabricating a thin film transistor having a silicon carbide buffer layer A method of making a thin film transistor is described incorporating the steps of forming a gate electrode, a layer of insulating material, a layer of buffer material, a layer of semiconductor material, a source electrode and drain electrode. The inventio... | 06/22/1993 |
| 5101242 | Thin film transistor A thin film transistor is described incorporating a gate electrode, a layer of insulating material, a layer of buffer material, a layer of semiconductor material, a source electrode and drain electrode. The invention reduces the problem of variation in th... | 03/31/1992 |
| 5060036 | Thin film transistor of active matrix liquid crystal display A thin film transistor of active matrix LCD comprising amorphous silicon layer formed on gate insulating layer and doped with phosphorous or boron, and insulating layer having two laminated structure and SiN layer formed between said two amorphous silicon... | 10/22/1991 |
