Class 257/E29.266 - With lightly doped drain or source extension (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E29.255. This subclass
No. of patents: 347
Last issue date: 04/29/2008

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Number	Title	Issue Date
7365361	Semiconductor device and method for manufacturing the same The present invention provides a method for manufacturing a semiconductor device, by which a transistor including an active layer, a gate insulating film in contact with the active layer, and a gate electrode overlapping the active layer with the gate insulating fil...	04/29/2008
7365402	LDMOS transistor An LDMOS semiconductor transistor structure comprises a substrate having an epitaxial layer of a first conductivity type, a source region extending from a surface of the epitaxial layer of a second conductivity type, a lightly doped drain region within the epitaxial...	04/29/2008
7335952	Semiconductor device and manufacturing method therefor To provide a semiconductor device that permits free setting of characteristics of individual semiconductor elements which are mixedly mounted and have different characteristics, and is free of steps between formed semiconductor elements, in a manufacturing method fo...	02/26/2008
7321155	Offset spacer formation for strained channel CMOS transistor A strained channel transistor and method for forming the same, the strained channel transistor including a semiconductor substrate; a gate dielectric overlying a channel region; a gate electrode overlying the gate dielectric; source drain extension (SDE) regions and...	01/22/2008
7306995	Reduced hydrogen sidewall spacer oxide An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a sp...	12/11/2007
7288814	Selective post-doping of gate structures by means of selective oxide growth A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spac...	10/30/2007
7271455	Formation of fully silicided metal gate using dual self-aligned silicide process An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of for...	09/18/2007
7265425	Semiconductor device employing an extension spacer and a method of forming the same A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also ...	09/04/2007
7247909	Method for forming an integrated circuit with high voltage and low voltage devices A method is disclosed for integrally forming at least one low voltage device and at least one high voltage device. According to the method, a first gate structure and a second gate structure are formed on a semiconductor substrate, wherein the first and second gate ...	07/24/2007
7214994	Self aligned metal gates on high-k dielectrics A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall ...	05/08/2007
7164189	Slim spacer device and manufacturing method A CMOS structure including a Slim spacer and method for forming the same to reduce an S/D electrical resistance and improve charge mobility in a channel region, the method including providing a semiconductor substrate including a polysilicon gate structure including...	01/16/2007
7129547	Method of fabricating a high performance MOSFET device featuring formation of an elevated source/drain region A method of fabricating a MOSFET device featuring a raised source/drain structure on a heavily doped source/drain region as well as on a portion of a lightly doped source/drain (LDD), region, after removal of an insulator spacer component, has been developed. After ...	10/31/2006
7126190	Self-aligned gate and method A semiconductor structure includes a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated by shallow trench isolation. Transistors are formed in the wells by fir...	10/24/2006
7091567	Semiconductor device including air gap between semiconductor substrate and L-shaped spacer and method of fabricating the same A semiconductor device includes source/drain regions, a gate pattern disposed on the semiconductor substrate between the source/drain regions, and L-shaped spacers that are used as masks in the forming of the source/drain regions. The L-shaped spacers each include a...	08/15/2006
6960807	Drain extend MOS transistor with improved breakdown robustness A drain-extended metal-oxide-semiconductor transistor (40) with improved robustness in breakdown characteristics is disclosed. Field oxide isolation structures (29c) are disposed between the source region (30) and drain contact regions (	11/01/2005
6703663	CMOS device using additional implant regions to enhance ESD performance and device manufactured thereby A method of forming a semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well comprises the following steps. Form over a substrate the combination of a gate oxide layer and a gate layer patterned into gate stacks with s...	03/09/2004
6700167	Semiconductor device having thick insulating layer under gate side walls A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the ga...	03/02/2004
6696729	Semiconductor device having diffusion regions with different junction depths An aspect of the present invention includes: a gate insulating layer formed on an n-type silicon semiconductor region; a gate electrode formed on the gate insulating layer; a channel region formed immediately below the gate electrode in the semiconductor ...	02/24/2004
6690060	Field effect transistor and method of fabricating the same by controlling distribution condition of impurity region with implantation of additional ion A first object of the present invention is to provide an insulated gate field effect transistor which realizes reductions in the junction depth and the resistance of source and drain junction regions beneath a gate electrode. Another object is to provide ...	02/10/2004
6677201	Method of fabricating thermal CVD oxynitride and BTBAS nitride sidewall spacer for metal oxide semiconductor transistors A method for using CVD oxynitride and BTBAS nitride during the sidewall formation process in MOS transistor fabrication processes. A silicon oxynitride layer (110) and a silicon nitride layer (120) are used to form sidewalls for MOS transistors. The silic...	01/13/2004
6677651	Semiconductor device and method for manufacturing the same A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the ga...	01/13/2004
6673663	Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ...	01/06/2004
6664600	Graded LDD implant process for sub-half-micron MOS devices A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N- LDD regions and N+ source and d...	12/16/2003
6660601	Semiconductor device and method for fabricating the same Ions of boron as a dopant are implanted using a gate electrode and an isolation film as a mask, thereby forming an ion-implanted layer as a prototype for an extended heavily doped layer. In this process step, a peak concentration of the dopant existing in...	12/09/2003
6660605	Method to fabricate optimal HDD with dual diffusion process to optimize transistor drive current junction capacitance, tunneling current and channel dopant loss Methods are discussed for forming a transistor comprising a source/drain region having both a graded HDD portion and a sharp HDD portion in a semiconductor substrate. The method comprises a dual diffusion process, wherein a gate structure is provided over...	12/09/2003
6661057	Tri-level segmented control transistor and fabrication method A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed ...	12/09/2003
6656824	Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch The present invention provides a method for fabricating low-resistance, sub-0.1 μm channel T-gate MOSFETs that do not exhibit any poly depletion problems. The inventive method employs a damascene-gate processing step and a chemical oxide removal etch to ...	12/02/2003
6649460	Fabricating a substantially self-aligned MOSFET The present invention includes methods and structures for forming at least a substantially self-aligned MOSFET. According to the present invention, a method of fabricating a semiconductor device includes providing a substrate; providing first materials (s...	11/18/2003
6642122	Dual laser anneal for graded halo profile Short-channel effects are controlled by forming abrupt, graded halo profiles. Embodiments include sequentially forming deep source/drain regions, ion implanting to form first deep amorphized regions, ion implanting an impurity into the first deep amorphiz...	11/04/2003
6638877	Ultra-thin SiO2using N2O as the oxidant N2 O is used as the oxidant for forming an ultra-thin oxide (14). The low oxidation efficiency of N2 O compared to O2 allows the oxidation temperature to be raised to greater than 850° C. while maintaining the growth rate...	10/28/2003
6630712	Transistor with dynamic source/drain extensions A method of fabricating an integrated circuit with a transistor having less susceptibility to off-state leakage current and short-channel effect is disclosed. The transistor includes high-K gate dielectric spacers and a T-shaped gate conductor. The high-K...	10/07/2003
6627504	Stacked double sidewall spacer oxide over nitride Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by recessing the silicon nitride spacers and forming barrier spacers on top of the silicon nitride spacers. The barrier...	09/30/2003
6620703	Method of forming an integrated circuit using an isolation trench having a cavity formed by reflowing a doped glass mask layer Isolation characteristics of an isolation trench can be enhanced. Elements to be isolated by an isolation trench (STI 2) are formed in active semiconductor regions shown by arrows 30 and 31 on a semiconductor substrate 1. The STI 2 is filled with SiOF....	09/16/2003
6620668	Method of fabricating MOS transistor having shallow source/drain junction regions A method of fabricating a MOS transistor having shallow source/drain junction regions is provided. A diffusion source layer is formed on a semiconductor substrate on which gate patterns are formed. Same type or different type of impurities are implanted i...	09/16/2003
6617219	Semiconductor device and method for lowering miller capacitance by modifying source/drain extensions for high speed microprocessors A method is provided, the method including forming a gate dielectric above a surface of the substrate, forming the conductive gate structure above the gate dielectric, the conductive gate structure having an edge region, and forming a source/drain extensi...	09/09/2003
6617229	Method for manufacturing transistor of double spacer structure A method for manufacturing a transistor of a double spacer structure is disclosed, in which a local LDD region is formed by forming a transistor including a gate electrode, and an oxide film spacer and a nitride film spacer formed sequentially, dry etchin...	09/09/2003
6614081	High-performance MOS transistor of LDD structure having a gate insulating film with a nitride central portion and oxide end portions A Metal Oxide Semiconductor (MOS) transistor includes a gate insulating film disposed on a surface of a silicon substrate. The gate insulating film has a central portion formed on the silicon substrate and comprising a nitride insulating film, and an end ...	09/02/2003
6586306	Method for fabricating semiconductor device A method for fabricating a semiconductor device is disclosed. In a high speed device structure consisting of a salicide, in order to fabricate a device having at least two gate oxide structures in the identical chip, an LDD region of a core device region ...	07/01/2003
6582995	Method for fabricating a shallow ion implanted microelectronic structure Within a method for fabricating a microelectronic fabrication comprising a topographic microelectronic structure formed over a substrate, there is implanted, while employing a first ion implant method and while masking a portion of the substrate adjacent ...	06/24/2003
6559016	Method of manufacturing low-leakage, high-performance device A method of manufacturing a low-leakage, high-performance device. A substrate having a gate electrode thereon is provided. A lightly doped, high-energy implantation is conducted to form a lightly doped source/drain terminal in the substrate. An offset spa...	05/06/2003

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Class 257/E29.266 - With lightly doped drain or source extension (EPO)