Bizarre Patents
Smoking Cessation Lighter and Method
A lighter for tobacco products suppresses the urge to smoke by operant conditioning.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7427775 | Fabricating strained channel epitaxial source/drain transistors The mobility of carriers may be increased in strained channel epitaxial source/drain transistors. Doped silicon material may be blanket deposited after removing ion implanted source/drain regions. The blanket deposition forms amorphous films over non-source/drain ar... | 09/23/2008 |
| 7368793 | HEMT transistor semiconductor device The semiconductor device of the present invention includes a device formation region formed on a substrate and including at least one semiconductor region, and a first electrode and a second electrode formed spaced apart from each other on the device formation regio... | 05/06/2008 |
| 7339236 | Semiconductor device, driver circuit and manufacturing method of semiconductor device The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS tr... | 03/04/2008 |
| 7339214 | Methods and apparatus for inducing stress in a semiconductor device Methods and apparatus are disclosed for selectively inducing stress in a semiconductor device, wherein a first region of a substrate is implanted so as to induce stress in a second region. An electrical device is formed at least partially in the second region, where... | 03/04/2008 |
| 7339215 | Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Carbon-doped silicon is then epitaxia... | 03/04/2008 |
| 7329914 | Charge trapping memory device with two separated non-conductive charge trapping inserts and method for making the same A charge trapping memory device with two separated non-conductive charge trapping inserts is disclosed. The charge trapping memory device has a silicon substrate with two junctions. A gate oxide (GOX) is formed on top of the silicon substrate and between the two jun... | 02/12/2008 |
| 7323752 | ESD protection circuit with floating diffusion regions This invention discloses an electrostatic discharge (ESD) protection circuit that comprises a substrate of a predetermined type, at least one MOS transistor being coupled to a pad of an integrated circuit for dissipating an ESD current from the pad during an ESD eve... | 01/29/2008 |
| 7279745 | Semiconductor device In a semiconductor device of the present invention, an N-type epitaxial layer 2 is deposited on a P-type substrate 1. In the epitaxial layer 2, a P-type diffusion layer 5 to be used as a back gate region is formed. An N-type diffusion lay... | 10/09/2007 |
| 7268399 | Enhanced PMOS via transverse stress In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regio... | 09/11/2007 |
| 7268398 | ESD protection cell with active pwell resistance control In an NMOS device, the turn-on voltage or the triggering voltage is reduced by adding an NBL connected to an n-sinker and contacted through an n+ region, which is connected to a bias voltage. The bias voltage may be provided by the drain contact or by a separate bia... | 09/11/2007 |
| 7259434 | Highly reliable amorphous high-k gate oxide ZrO2 A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Also shown is a gate oxide with a conduction band offset in a range of approximately ... | 08/21/2007 |
| 7256432 | Field-effect transistor An electric-field control electrode (5) is formed between a gate electrode (2) and a drain electrode (3). A multilayered film including a SiN film (21) and a SiO2 film (22) is formed below the electric-field control elec... | 08/14/2007 |
| 7217963 | Semiconductor integrated circuit device In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargemen... | 05/15/2007 |
| 7176526 | Semiconductor device, method for producing the same, and information processing apparatus A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103, pa... | 02/13/2007 |
| 7160769 | Channel orientation to enhance transistor performance P channel transistors are formed in a semiconductor layer that has a (110) surface orientation for enhancing P channel transistor performance, and the N channel transistors are formed in a semiconductor layer that has a (100) surface orientation. To further provide ... | 01/09/2007 |
| 7138690 | Shielding structure for use in a metal-oxide-semiconductor device An MOS device is formed comprising a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semicon... | 11/21/2006 |
| 7078761 | Nonvolatile memory solution using single-poly pFlash technology A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the ... | 07/18/2006 |
| 6699760 | Method for growing layers of group III-nitride semiconductor having electrically passivated threading defects One method includes epitaxially growing a layer of group III-nitride semiconductor under growth conditions that cause a growth surface to be rough. The method also includes performing an epitaxial growth of a second layer of group III-nitride semiconducto... | 03/02/2004 |
| 6696323 | Method of manufacturing semiconductor device having trench filled up with gate electrode In a semiconductor device, a p-type base region is provided in an n- -type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+ -type source region extends in the ... | 02/24/2004 |
| 6690042 | Metal oxide semiconductor heterostructure field effect transistor A method and structure for producing nitride based heterostructure devices having substantially lower reverse leakage currents and performance characteristics comparable to other conventional devices. The method and structure include placing one or more l... | 02/10/2004 |
| 6686245 | Vertical MOSFET with asymmetric gate structure A semiconductor fabrication process and structure in which a semiconductor channel structure (140) having first and second major surfaces perpendicular to a semiconductor substrate (102) is formed overlying and electrically isolated from the substrate (10... | 02/03/2004 |
| 6683345 | Semiconductor device and method for making the device having an electrically modulated conduction channel A semiconductor device having a conduction channel which is electrically modulated. A trench structure is formed within a substrate enclosing a diffusion region. The trench structure isolates the devices formed within the diffusion region from the remaini... | 01/27/2004 |
| 6680503 | Field-effect transistor structure with an insulated gate The field-effect transistor has an insulated gate, a source electrode, a drain electrode, and an inversion channel between the source and drain electrodes and underneath the gate electrode. The gate electrode is fabricated from a material which does not h... | 01/20/2004 |
| 6680244 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device comprises the steps of forming a gate oxide film on a surface of a semiconductor substrate, subjecting the gate oxide film to a nitriding treatment, forming a gate electrode film over the surface of the se... | 01/20/2004 |
| 6670250 | MOS transistor and method for forming the same A MOS transistor including a gate poly oxide layer formed to have different thicknesses over the entire surface of a semiconductor substrate and a method for forming the MOS transistor are provided. A gate oxide layer pattern and a gate conductive layer p... | 12/30/2003 |
| 6670260 | Transistor with local insulator structure A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The... | 12/30/2003 |
| 6661277 | Enhanced conductivity body biased PMOS driver According to one embodiment of the present invention a method for biasing a body of a transistor. The method includes detecting a voltage applied to a terminal of a transistor and coupling a biasing voltage to the body based upon the detected voltage.... | 12/09/2003 |
| 6650171 | Low power operation mechanism and method An apparatus and method are provided for powering a chip having at least one transistor. A voltage regulating device may apply a first voltage and a second voltage to the transistor. The voltage regulating device may include a mechanism to apply a third v... | 11/18/2003 |
| 6642577 | Semiconductor device including power MOSFET and peripheral device and method for manufacturing the same First and second trenches are formed on an n+ type substrate at a power MOSFET formation region and a peripheral device formation region, respectively. An n- type epitaxial film, a p type epitaxial film, and an n+ type epi... | 11/04/2003 |
| 6642591 | Field-effect transistor A field-effect transistor includes a silicon substrate on which is formed a channel region, a source region and a drain region. A gate insulation layer of a transition metal oxide having a perovskite structure is formed over at least the channel region, a... | 11/04/2003 |
| 6639450 | Enhanced conductivity body biased PMOS driver According to one embodiment of the present invention a method for biasing a body of a transistor. The method includes detecting a voltage applied to a terminal of a transistor and coupling a biasing voltage to the body based upon the detected voltage.... | 10/28/2003 |
| 6624045 | Thermal conducting trench in a seminconductor structure and method for forming the same The invention relates to a method of forming a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the method includes filling a portion of the trench with a thermally conducting material and patterning a co... | 09/23/2003 |
| 6617653 | MISFET P-type active region 12; n-type source/drain regions 13a and 13b; gate insulating film 14 made of a thermal oxide film; gate electrode 15; source/drain electrodes 16a and 16b, are provided over a p-type SiC substrate 11. In the active region 12, p-type he... | 09/09/2003 |
| 6613637 | Composite spacer scheme with low overlapped parasitic capacitance A method and composition for a composite spacer with low overlapped capacitance includes a low-k dielectric spacer layer. A first spacer is deposited on a partially formed semiconductor device having a gate oxide stack, followed by a low dielectric consta... | 09/02/2003 |
| 6613622 | Method of forming a semiconductor device and structure therefor A semiconductor device (10, 40) is formed to have a well (19) in a substrate (11). The well and the substrate have the same doping type, for example both P-type or both N-type. Low resistance contact regions (26, 27) of a second conductivity type are form... | 09/02/2003 |
| 6570239 | Semiconductor device having resistive element A trench is formed in an n+ type substrate in a vertical direction from a main surface of the substrate, and a p type layer is deposited in the trench to have a recess portion. An n+ type layer is embedded in the recess portion. Acco... | 05/27/2003 |
| 6528373 | Layered dielectric on silicon carbide semiconductor structures A dielectric structure is disclosed for silicon carbide-based semiconductor devices. In gated devices, the structure includes a layer of silicon carbide, a layer of silicon dioxide on the silicon carbide layer, a layer of another insulating material on th... | 03/04/2003 |
| 6515348 | Semiconductor device with FET MESA structure and vertical contact electrodes A semiconductor device comprises one or more field effect devices (FD) having source and drain regions (5 and 6) spaced apart by a body region (3a). A gate structure (7a, 7b), preferably in a trench (4), controls a conduction channel in a portion (3b) of ... | 02/04/2003 |
| 6515319 | Field-effect-controlled transistor and method for fabricating the transistor An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the sem... | 02/04/2003 |
| 6495407 | Method of making an article comprising an oxide layer on a GaAs-based semiconductor body A novel method of forming a GaAs-based MOS structure comprises ion implantation after oxide formation, and subsequent slow heating and cooling, carried out such that essentially no interfacial defects that are detectable by high resolution transmission el... | 12/17/2002 |
